Dr. Khalid Javeed
Assistant Professor
Department of Computer Engineering University of Sharjah
[email protected] m[email protected]
Cell: +971-524917531
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Professional academician and dedicated researcher aim to impart quality knowledge and provide cutting edge solutions to society and communities.
Research Interests
Specialized Memory Architectures, Cryptographic Engineering, Hardware Security, Computer Arithmetic
& Architecture, Deep Neural Networks for Embedded Systems, Hardware Acceleration of Bioinformatics, Machine Learning and Cryptographic Algorithms.
Professional Association
Member (registered Engineer), Pakistan Engineering Council (PEC # COMP4455) Member, Institute of Electrical and Electronics Engineering (IEEE)
Qualification
Ph.D. Computer Engineering
Dublin City University – Dublin, Ireland
Dissertation: Efficient Hardware Architectures for Scalar Multiplications on Elliptic Curves over Prime Field
March 2012-June 2016 Public Defense
MS. System on Chip Design
Linkoping University - Linkoping, Sweden Sep 2008-Sep 2010 CGPA = 3.4/04
BS Computer Engineering
COMSATS University, Abbottabad Campus - Pakistan March 2003-March 2007 CGPA = 3.56/04
Work Experience
University of Sharjah, UAE Assistant Professor
Department of Computer Engineering
August 2022-Present
Research Fellow (Marie Curie researcher)
https://lero.ie/people/khalid-javeed
Trinity College Dublin- Dublin, Ireland (Ranked among Top 100)
Project: Hardware acceleration of Crypto. and DNNs algorithms. July 2021-July 2022
Bahria University Islamabad, Pakistan Associate Professor
Department of Computer Engineering
http://www.bahria.edu.pk/buic/ce/dr-khalid-javed-2/
June 2021-July 2021
Bahria University Islamabad, Pakistan Head of Department & Assistant professor Department of Computer Engineering http://www.bahria.edu.pk/buic/ce
June 2018-Nov 2020
Bahria University Islamabad, Pakistan Assistant professor & Accreditation Coordinator Department of Computer Engineering
http://www.bahria.edu.pk/buic/ce
Aug 2017-June 2018
COMSATS University Islamabad, Pakistan Assistant professor
Department of Electrical & Computer Engineering July 2016-July 2017 Dublin City University, Dublin, Ireland
Tutor & Lab demonstrator
School of Electronics Engineering June 2012-March 2016
COMSATS University Islamabad, Pakistan Lecturer
Department of Electrical & Computer Engineering Sep 2010-March 2012 COMSATS University Islamabad, Pakistan
Lecturer
Department of Electrical & Computer Engineering June 2007-Sep 2008
Teaching Interests
Digital logic design, computer architecture, HDL languages (Verilog & VHDL), microprocessor systems, embedded systems, data communication, computer networks, basic and advanced programming courses (C, C++, python), Artificial Intelligence etc.
Some of the taught courses are:
Course Code Course Name Level
CSC-320 Operating Systems BS Computer Engineering
ESC 705 Research Methodologies PhD Computer Engineering ESC 507 Research Methodologies MS Computer Engineering CEN 720 Advanced Computer Architecture MS Computer Engineering CEN 742 Advanced Digital System Design MS Computer Engineering EEN 224 Electronic Devices and Circuits BS Computer Engineering
CEN 120 Digital Logic Design BS Computer Engineering
EEN 313 Signals and Systems BS Computer Engineering
CEN 442 Digital System Design BS Computer Engineering
CEN 439 Embedded System Design BS Computer Engineering CEN 321 Microprocessors and Interfacing BS Computer Engineering
Administrative skills & Achievements
Head of computer Engineering Department Bahria University Islamabad http://www.bahria.edu.pk/buic/ce/dr-khalid-javed-2/
Being Head of Department (HoD) between June 2018-Nov 2020, I was responsible for all the academic and administrative activities of the department and directly reporting to the Dean faculty of engineering sciences. The department offers Computer Engineering programs at BS, MS and Ph.D. levels. BS computer engineering program has received International Accreditation under Washington Accord Outcome Based Education (OBE) through Pakistan Engineering Council (PEC). As, HoD, I have significant contributions particularly in achieving this milestone and participated actively at different statutory bodies at department, faculty and the University level.
• Head of Departmental Board of Studies (DBOS) Department level
• Head of Departmental Research Committee (DRC) Department Level
• Member of Faculty Research Committee (FRC) Faculty Level
• Member of the Faculty Board of Studies (FBOS) Faculty Level
• Member of Academic Council Meeting (ACM) University Level
• Member of Higher Education Research Committee (HERC) University Level Some of the academic contributions as HoD were:
• Successfully conducted/managed accreditation visits for BS and MS programs
• Curriculum development for MS Computer Engineering program
• Curriculum development for BS Computer Engineering program
• Revised department Vision & Mission and devised overall OBE framework
• Defined learning outcomes at courses and program levels (BS computer engineering)
• Defined rubrics-based lab grading mechanism
• Defined KPIs for attainment of learning outcomes
• Defined a continuous quality improvement cycle at course and program levels (BS computer engineering)
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Students Supervision
Ph.D. students Co-Supervisor
Dr. Yasir Ali, Efficient Hardware Accelerator for Elliptic
Curve Point Multiplication. Graduated
MS Students
1. Usama Razaq, hardware acceleration of DNA sequence alignment
2. Saifuallah Khan, Full word Montgomery Multiplier for ECC Application
3. Zeeshan Haider, Low-cost built-in test architecture Integrated with PRESENT cipher Core
4. M. Huzaifa, Efficient Modular Multipliers for Public Key Cryptography
Graduated
5. M. Shabbar, Hardware Implementation of Feed Forward Neural Networks.
6. Waqas Ahmad, Validation of Secure Data Wiping Tools for Android Phones
BS Final Year projects 1. Hussain Bangash and Mahjabeen, Timing attacks implementation, analysis and countermeasures
2. Usama Razaq and Hussain Ahmad, Home monitoring and parental control system
3. Mohtashim and Ayesha Yaqoob, Embedded System for Monitoring using DNNs.
Graduated
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Technical & Communication Skills
Technical Skills
Circuit and system level optimization of cryptographic primitives, Verilog and VHDL languages for digital design, Xilinx & Vivado Design Suite for prototyping on Xilinx FPGAs, Software implementation of cryptographic algorithms using C++ and C#, Python languages, Cadence & Microwind tools for full- Custom IC design, Assembly language for Micro-controllers and Matlab for signal processing algorithms, GNU plot, MS excel, MS Word and Latex for documentation.
Communication Skills
excellent command on English language, excellent presentation & Interpersonal skills, team leader and management skills
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Professional Activities
• Reviewer Journal of Circuit, theory and applications
• Reviewer IEEE transaction on Circuit and System II
• Reviewer IEEE transaction on VLSI
• Reviewer IEEE Embedded Systems Letter
• Reviewer Journal of Distributed system and sensor networks
• Reviewer Microprocessors and Microsystems: Embedded Hardware Design
• Examiner MS and PhD thesis at different Higher Education Institutes of Pakistan
• Program Evaluator (PE) of Higher Education Commission, Pakistan
• Attended Workshop on Outcome Based Education, Washington Accord
• Attend 1st and 2nd PEC Deans Conference on Outcome Based Education and Reforms
• Attended Two Weeks Faculty Development Training at COMSATS and Bahria Universities.
Conference/Workshop Organization/Lab Development
• Design/Develop Computer Vision Laboratory with state-of-the-art equipment at Bahria University
• Upgraded Applied Physics & Electronics Laboratory at Bahria University
• Chair and Head of Organization Team: Open Source Summit (OSS’18) Department of Computer Engineering, Bahria University.
• Member Organization Team: IEEE International Conference on Communication, Computing, and Digital Systems (C-CODE’19).
Project Funding
• Secure Marie Curie post-doc fellowship award of euro 136000. This is very competitive process, where project proposal goes through international review and interview stages before approval.
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11 Million PKR project as Principal Investigator (hardware optimization of DNNs for Embedded Systems) has been submitted in recent HEC NRPU call. It is under review stage.Journal Publications
https://scholar.google.com.pk/citations?user=GPJb34wAAAAJ&hl=en
1. Shah, Y.A., K. Javeed, S. Azmat, and M. Imran, LUT-based High Speed Point Multiplier for Goldilocks-Curve448, to appear in IET Computer & Digital Techniques, 2020 (IF 0.8)
2. Haider, Z., K. Javeed, M. Song, and X. Wang, A Low-Cost Self-Test Architecture Integrated With PRESENT Cipher Core. IEEE Access, 2019. 7: p. 46045-46058. (IF 4.09)
3. Shah, Y.A., K. Javeed, S. Azmat, and X. Wang, Redundant-Signed-Digit-Based High Speed Elliptic Curve Cryptographic Processor. Journal of Circuits, Systems and Computers, 2019. 28(05): p.
1950081. (IF 0.6)
4. Khan, S., K. Javeed, and Y.A. Shah, High-speed FPGA implementation of full-word Montgomery multiplier for ECC applications. Microprocessors and Microsystems, 2018. 62: p. 91-101. (IF 1.04) 5. Shah, Y.A., K. Javeed, S. Azmat, and X. Wang, A high‐speed RSD‐based flexible ECC processor
for arbitrary curves over general prime field. International Journal of Circuit Theory and Applications, 2018. 46(10): p. 1858-1878. (IF 1.55)
6. Liu, P., X. Wang, S. Chaudhry, and K. Javeed, Secure video streaming with lightweight cipher PRESENT in an SDN testbed. CMC 2018. (IF 3.024)
7. Javeed, K., X. Wang, and M. Scott, High performance hardware support for elliptic curve cryptography over general prime field. Microprocessors and Microsystems, 2017. 51: p. 331-342.
(IF 1.04)
8. Javeed, K. and X. Wang, Low latency flexible FPGA implementation of point multiplication on elliptic curves over GF (p). International Journal of Circuit Theory and Applications, 2017. 45(2):
p. 214-228. (IF 1.55)
9. Javeed, K. and X. Wang, FPGA based high speed SPA resistant elliptic curve scalar multiplier architecture. International Journal of Reconfigurable Computing, 2016. 2016: p. 2.
10. Chen Mo, X. Wang, M. He, L. Jin, K. Javeed, A Network Traffic Classification Model Based on Metric Learning. in CMC 2020. (IF 3.024)
Submitted
• K. Javeed, Khan, S., and X. Wang, A Review on Hardware implementation of Montgomery based Modular Multiplier, IEEE Access.
• K. Javeed, Khan, S., and X. Wang, High Speed Parallel Reconfigurable Modular Multipliers for ECC Applications, International Journal of Circuit Theory and Applications.
Conference Publications
1. Z. Abideen., S. Khan, and Javeed. K. Interference Management in Ad Hoc Networks. in 2019 International Conference on Engineering and Emerging Technologies (ICEET). 2019.
2. Shah, Y.A., S. Khan, Javeed. K, and S. Azmat. A high speed redundant-signed-digit based montgomery modular multiplier. in 2018 International Conference on Engineering and Emerging Technologies (ICEET). 2018. IEEE.
3. Javeed, K., D. Irwin, and X. Wang. Design and performance comparison of modular multipliers implemented on FPGA platform. in International Conference on Cloud Computing and Security.
2016. Springer.
4. Javeed, K. and X. Wang, Speed and Area Optimized Parallel Higher-Radix Modular Multipliers. IACR Cryptology ePrint Archive, 2016. 2016: p. 53.
5. Javeed, K., X. Wang, and M. Scott. Serial and parallel interleaved modular multipliers on FPGA platform. in 2015 25th International Conference on Field Programmable Logic and Applications (FPL). 2015. IEEE.
6. Javeed, K. and X. Wang. Efficient montgomery multiplier for pairing and elliptic curve based cryptography. in 2014 9th International Symposium on Communication Systems, Networks &
Digital Sign (CSNDSP). 2014. IEEE.
7. Javeed, K. and X. Wang. Radix-4 and radix-8 booth encoded interleaved modular multipliers over general F p. in 2014 24th International Conference on Field Programmable Logic and Applications (FPL). 2014. IEEE.
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Awards/Honors
• Post-doc fellowship award under Marie Curie funding at school of Compuer Science Trinity College Dublin, Ireland.
• PhD fellowship award, Higher Education Authority (HEA) Ireland under Telcommunication Graduative Scheme (2012-2016).
• MS Scholarship for Sweden (2008-2010), Higher Education Comission (HEC) Pakistan.
• BS Computer Engineering (2003-2007) Scholarship (Top 3 student of class) from COMSATS University Islamabad.
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References
Prof. David Gregg Professor, School of Computer Science, Trinity College Dublin, Ireland [email protected] Prof. Dr. M. Najam-Ul-Islam
Professor/Ex. Dean Faculty of Engineering sciences Bahria University Islamabad, Pakistan
[email protected] Dr. Xiaojun Wang
Associate Professor School of Electronics Engineering Dublin City
University Ireland [email protected]