Pipelining – Data hazard
Computer Organization &Architecture – 14032205 Umm Al-Qura University
1441H
Graphical Representation of MIPS 5-stage Pipeline
• Consider add instruction
read write
Data Hazards
• An instruction depends on completion of data access by a previous instruction
• add $s0, $t0, $t1
sub $t2, $s0, $t3
Forwarding
• Use result when it is computed
• Don’t wait for it to be stored in a register
• Requires extra connections in the datapath
Load-Use Data Hazard
• Can’t always avoid stalls by forwarding
• If value not computed when needed
• Can’t forward back in time!!!
• lw $s0, 20($t1)
sub $t1, $s0, $t3
Code Scheduling to Avoid Stalls
• Reorder code to avoid use of load result in next instruction
• C code for A = B + E; C = B + F;
lw $t1, 0($t0) lw $t2, 4($t0)
add $t3, $t1, $t2 sw $t3, 12($t0)
lw $t4, 8($t0)
add $t5, $t1, $t4 sw $t5, 16($t0)
stall
stall
lw $t1, 0($t0) lw $t2, 4($t0) lw $t4, 8($t0)
add $t3, $t1, $t2 sw $t3, 12($t0)
add $t5, $t1, $t4 sw $t5, 16($t0)
11 cycles 13 cycles
Dependencies
Data Hazards
• Consider the following code sequence:
sub $2, $1,$3 and $12,$2,$5 or $13,$6,$2 add $14,$2,$2 sw $15,100($2)
• We can resolve hazards with forwarding
• Assume only add, sub, AND, OR instructions to forward
• How do we detect when to forward?
Dependencies and Forwarding
$2 value changes from 10 to -20 during middle of CC5
when sub inst. writes its result
add & sw would get the correct value of -20
(NO HAZARDS) and & or would get the incorrect value of $2
(HAZARDS)
The desired result is available at end of EX stage or CC3
four instructions Depend on the result in register $2
$2 had the value 10 Before sub inst.
lines going backward refer to data hazards
• and needs $2 result in CC 4
• or needs $2 result in CC5
Dependencies and Forwarding
Solution:
forward data as soon as it is available to any units that need it before it is available
to read from register file
Detecting When to Forward
• Pass register numbers along pipeline
• e.g., ID/EX.RegisterRs means register number for Rs sitting in the ID/EX pipeline register
• Note that ALU operand register numbers in EX stage are given by
• ID/EX.RegisterRs, ID/EX.RegisterRt
ID/EX EX stage
Detecting When to Forward
Data hazards when:
Forward from EX/MEM pipeline register
1a. EX/MEM.RegisterRd = ID/EX.RegisterRs 1b. EX/MEM.RegisterRd = ID/EX.RegisterRt
Ver y im por tan t
Detecting When to Forward
EX/MEM.RegisterRd = ID/EX.RegisterRs = $2 Can be detected when
sub instruction is in MEM stage and instruction is in EX stage
Hazard 1a
This hazard is between �� ��
IF/ID ID/EX
IF/ID
EX/MEM
ID/EX
1a. EX/MEM.RegisterRd = ID/EX.RegisterRs
Detecting When to Forward
Hazard 2b
This hazard is between ��
t
Can be detected when sub instruction is in WB stage or instruction is in EX stage
2b. MEM/WB.RegisterRd = ID/EX.RegisterRt
Detecting When to Forward
• Destination register could be Rd or Rt.
• Will use Rd to indicate both cases
• Not enough to check if Rd == (Rs or Rt)
• Some instructions do not write a register (such as sw)
• (i.e. sometime it would forward when it shouldn’t)
• Also, avoid writing register 0 (ex. sll $0, $1, 2)
• So, only Forward
1) if instruction will write to a register (i.e. check if RegWrite signal is active)
• EX/MEM.RegWrite, MEM/WB.RegWrite
2) if Rd for that instruction is not $zero
• EX/MEM.RegisterRd ≠ 0,
• MEM/WB.RegisterRd ≠ 0
Ex. sw $s1, 12($t1)
add $s2, $s1, $s3 Is this a hazard?
Adding Forwarding
• datapath without forwarding • datapath With forwarding
00 01 10 00 01 10
Data to be forwarded FW unit is
implemented at EX stage
Forwarding Conditions
• EX hazard
• if (EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠ 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRs)) ForwardA = 10
• if (EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠ 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRt)) ForwardB = 10
• MEM hazard
• if (MEM/WB.RegWrite and (MEM/WB.RegisterRd ≠ 0) and (MEM/WB.RegisterRd = ID/EX.RegisterRs)) ForwardA = 01
• if (MEM/WB.RegWrite and (MEM/WB.RegisterRd ≠ 0) and (MEM/WB.RegisterRd = ID/EX.RegisterRt)) ForwardB = 01
00
01
10
00
01
10
Load-Use Data Hazard
Need to stall
for one cycle Need Hazard Detection Unit!!!
Value of $s2 is forwarded from MEM/WB to EX stage
Hazard
Load-Use Hazard Detection
• Hazard detection unit operates during ID stage, so, it can insert stall between lw and its use
• ALU operand register numbers in ID stage are given by
• IF/ID.RegisterRs, IF/ID.RegisterRt
• Load-use hazard when
• ID/EX.MemRead and
((ID/EX.RegisterRt = IF/ID.RegisterRs) or (ID/EX.RegisterRt = IF/ID.RegisterRt))
• If detected, stall and insert bubble, i.e. stall 1cc
Test if the inst. is lw
The only inst. that reads data mem. is lw
Check if destination register field of lw in EX stage
matches either source register of inst. in ID stage
• stalling the dependent instruction (and) in the Decode stage.
• and enters the Decode stage in cycle 3 and stalls there through cycle 4.
• The subsequent instruction (or) must remain in
the Fetch stage during both cycles as well, because
the Decode stage is full.
• In cycle 5, the result can be forwarded
from the WB stage of lw to the EX stage of
and .
• In cycle 6, source $s0 of the or inst. is read directly
from the register file, with no need for forwarding
• EX stage is unused in cycle 4.
• MEM stage is unused in Cycle 5
• WB is unused in cycle 6.
• stall the pipeline: holding up operation until the data is available
unused stage propagating
through the pipeline is called
a bubble, and it behaves like
a nop instruction
Stall/Bubble in Pipeline
The hazard forces and & or instructions to repeat
in clock cycle 4 what they did in clock cycle 3
How to Stall the Pipeline
1) Force control values in ID/EX register to 0
• EX, MEM and WB do nop (no-operation)
2) Prevent update of PC and IF/ID register
• instruction in ID stage is decoded again (in our example and $4, $2, $5)
• Instruction in IF stage is fetched again (in our example or $8, $2, $6)
• 1-cycle stall allows MEM to read data for lw
• Can subsequently forward to EX stage
(Set all 9 control signals to 0)
Datapath with Hazard Detection
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Hazard d
etection
unit is implem
ented in
the ID stage
P re ve n ts P C f ro m c h an gi n g: i.e . f et ch t h e s am e in st ru cti o n P re ve n ts IF /I D f ro m c h an gi n g: i.e . d ec o d e th e sa m e in st ru cti o n ID/EX pipeline register is cleared to prevent information from propagating forward
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