Midterm Exam

(1)

Umm Al-Qura University

Computer Engineering Department

Basics of Integrated Circuits Design ةلماكتملا رئاودلا ميمصت ءيدابم

1403364 – 3

Midterm Exam

Student Name:

Student ID:

Problem Max Score

1 10

2 10

3 10

4 10

Total 40

Bonus 10

Modified Total

Best Wishes

Dr Adnan Gutub

n

i

≈ 10 cm q ≈ 1.6×10

^-19

C μ

n

≈2.5μ

p

V

t

≈25mV υ

d

≈µ 

σ ≈ q(nμ

n

+ pμ

p

)



F(gate)

≈±0.55V C

ox

≈ 

ox

/t

ox

Q

_ox

≈ q . N

_ox

V

bi

≈ V

t

ln (N

A

N

D

/n

i2

) Å=10

^-10

meter

f = 10

^-15

p = 10

^-12

n = 10

^-9

µ = 10

^-6

m = 10

^-3

k = 10

³

M = 10

⁶

G = 10

⁹



Si

≈ 12×8.85×10

^-14

F/cm



SiO2

≈ 4×8.85×10

^-14

F/cm

) / ln(

.

) / ln(

. ) (

i D t

A i t

n N V

N n V Substrate

F







GC

≈ 

F(substrate)

- 

F(gate)

) (

0 2 _Si _S2 _F_Substrate

B q N

Q   

V

T0

≈

GC

-2

F

-Q

B0

/C

ox

-Q

ox

/C

ox



 

  



 _T₀ 2 _F₍_Substrate₎ _SB 2 _F₍_Substrate₎

T V V

V   

ox S Si

C N q

  ²

I

_D

(lin)=μC

ox

(W/L)[(V

_GS

-V

_T

)V

_DS

– {(V

DS

)

²

/2}]

I

D

(sat)=(1/2) μC

ox

(W/L)[(V

GS

-V

T

)

²

]

ax

²

+bx+c = 0  

a ac b

x b

2

 4



 

(2)

Problem 1

(10 points)

Observe the two MOS structures under external bias. One has N-type Si Substrate and the other has P-type substrate.

Specify the operating region (accumulation, depletion, inversion) if: (4 points)

a)

Va > 0 ? (small)

b) Va >> 0 ? (large)

c)

Va < 0? (small)

d)

Va << 0 ? (large)

e)

Va > 0 ? (small)

f) Va >> 0 ? (large)

g)

Va < 0? (small)

h)

Va << 0 ? (large)

A Si MOS Transistor having its substrate doped with 34×10¹⁵ cm^-3 Acceptors and 235×10¹⁴ cm^-3 Donors. The MOS gate is heavily doped with 10²⁰ cm^-3 Donors. Use: Nox= 3125×10⁸ cm^-2 , F(substrate) = - 0.35 v, _F(gate)= - 0.55 v, Cox = 10^-7 , QB0 = -4.88×10^-8, Find:

i) Substrate (Bulk) major carrier and its net concentration? (6 points)

j) Gate type?

k) GC ?

l) Qox ?

m)

V

_T0 ?

n) What is the type of transistor ?

Va Gate (Metal) Si (P-Type)

Oxide (SiO2)

Va Gate (Metal) Si (N-Type)

Oxide (SiO2)

(3)

P N

5µm 9µm

Va=5V

conductor 1k

I

Observe the P-N Junction with its hole mobility 300 cm²/(v.s). It is made by first doping the complete Si bar with Donors of concentration 5×10¹² cm^-3, then, one side is doped with Acceptors of concentration of 2×10¹⁷ cm^-3 forming the P-Side.

a) Calculate the built-in potential of the junction? (2 points)

b) Calculate the resistivity of the P-side? (1 point)

c) Calculate the resistivity of the N-side? (1 point)

d) Using the same P-N junction from above in the circuit shown calculate the current I ? (6 points)

(4)

Problem 3

(10 points)

a)

Fill the table below with the parameter values generated by scalling by a factor of S:

Quantity Before Scalling

After Scalling Full Scalling

(Constant-Field Scalling) Constant-Voltage Scalling

Channel length L

Channel width W

Gate oxide thickness tox

Junction depth xj

Power supply voltage VDD

Threshold voltage Vt

Doping densities

NA

ND

Oxide capacitance Cox

Drain current ID

Power dissipation per device P

b)

Match clearly between the following:

Drain Induced Barrier Lowering (DIBL) Very thin oxide layer causing contact

between the gate and substrate.

Decrease in Vth

Electrons inject into the oxide damaging it near the drain junction.

Pin holes A main problem due to making the

channel short.

Hot Carriers Current leakage between source and

drain without the gate control.

Transmission Line effect

Substrate between different transistors may act as channels connection which are unwanted.

c)

Draw the N-channel MOSFET model that shows all capacitance effects?

d)

Draw a figure of the total oxide capacitance vs. V

_GS

, Show an overall behaviour graph?

Total Oxide Capacitance

V

_GS

(5)

W/L=10

Vin

Vout

10M

Study the inverter circuit shown assuming: Vth =1v, Cox =10^-4 F/m², µn=2×10^-4 m²/(v.s).

a) Calculate Vout for Vin = 0.5 v?

b) Calculate Vout for Vin = 2 v?

c) Calculate Vin for Vout = 1.5 v?

(6)

(7)

+ 5v.

+ 3.5v

+ 5v.

+ 4.5v

+ 5v.

+

5v

+ 5v.

+2v.

1-Define the type of transistor (NMOS-Enhancement, NMOS-Depletion, PMOS)?

2-Write the labels (G,D,S) on the transistor nodes shown based on voltages given?

3-Derive the operation mode (Cut-off, Saturation, Linear)?

4-Calculate the current passing through every transistor based on conditions given?

Transistor Type:

The operation Mode :

Calculate current value =

Transistor Type:

ID(sat)=(1/2) μCox(W/L)[(VGS-VT)] Assume |Vt| = 1, µCox = 10^-7 F/(v.s), and W/L=1, for all transistors shown.

(8)

+ 3v.

+ 5v

+4.5v

+ 5v

+1v

+ 5v

+1v

+1.7 v

Transistor Type: