j g ^ f i ' ^ i n e I V»li»niA<»il<iTOMSd.nc..naT.ctn.logy A d r o a , in NU»M S o m r a : Nanoroene. tmtS NmolKhnology
AAt, Mat c«. . •._ • ' — V. Nat So,: Nanosa. Nanoteehnol
7 (2016) (eSOn (6pp) (fo, ,0 1086/2043^62/7/2/025011
A complete analytical potential based
solution for a 4H-SiC MOSFET in nanoscale
M K Yadav, K P Pradhan and P K Sahu
Department of Becnicsi Eniinrering. NadoBd Institute of Technology, Rouitela, 769008. CMishi India E-mail: niymanojyadav578®gmall.com, k.p.pnidhan«ieee.ois anii pksimu(»nitrld.ac.in Received 23 March 2016
Accepted for publication 26 April 2016 Pubhshed 24 May 2016 Abstract
Analytical modeling with a verified simulation setup of surface potential, threshold voltage and etaitnc Seld for a 4H-SiC MOSFET is presented to make enquiries about the short chaimel effects. The two-dmiensional (2D) Poisson equation is used to achieve the model for surface poteiltial. The 2D position equations have been solved by using four boundary conditions The detail of the model is appraised by the various MOSFET parameteis such as silicon carbide thickness, body doping concenttation, and gale oxide mflueneing the elecmc field channel potential and threshold voltage. The outcome shows dial this model can teduce the short chamiel effects, drain mduced bamer lowering and advance the sub-threshold fiilfiUment in nanoelectronic apphcadons as compaied to silicon MOSFETs. By comparing die model results wiOi die 2D device simulations the veracity of the suggested 2D analytical model is proven.
Keywords: MOSFET. 4H-SiC, short channel effects, 2-dimensionaI modefing Classification numbers; 2.07, 3.02, 5.01, 6.01
1. Introduction MOSFETs are die power MOSFETs devices Uiat have low
•JiU.-^n ....I, .1 r^r--. -. „ .. switching losses and tiiat can deliver low conducnon WiUl Stlicon carbide (SiC) was accidentally discovered in 1890 by high breakdown votoges [4). At Uie present time, SiC power E G Acheson, an assistant to Thomas Edison [1], SiC is a MOSFETs widl breakdown voltages fiomSOO-ISOOV 13] are compound semiconductor and is a mixture of siUcon and readily available. SiC devices can also be made to have a carbon witii die chemical fonnula SiC Silicon is covalently much Uiinner drift layer, and greater doping concentration i e bonded wiUi carbon. In 4H-SiC, 4H is wntten in die Ramsdell die breakdown area for SiC is 2 4 MV cm^' compared to classiftcation scheme where die number indicates die layer silicon dial has a breakdown disciphne of 0.25 MV cm"' [3) and the letter indicates die Biavais lattice (21. That means in a That means die breakdown field for silicon is ten times lesser 4H-SlC stiiicnne four hexagonal layers of SiC are present. *an SiC [4]. Electinn mobility (/t) for SiC is 950cm- V " ' Sic exists m a kind of polymorphic ctysuiljine building ^ ' [4] compared to sUicon, fi = 1400cm^V"' s"' [5]. This known as a polytype, e.g. 3C-SiC, 4H-SiC, 6H-S1C [2], analogy shows diat electron mobility for SiC is significantiy Presentiy 4H-SiC is usually prefeired in power device man- ' " ^ ^ compared to silicon. The continuous shrinkage of tile ufacturing. SiC is a wider band-gap (E^) material witii ^^^^'^'^ ^^y require tile attainment of excessive packing f, = 3.3 eV [31 as compared to silicon lE^ = 1.1 eV). Hence '*'="s'^ ^ ' ^ higher efficiency. However, tile devaluation of tile SiC has a band-gap diree times higher tiian silicon. Due to its '^'^"^^ dimensions in aU fonns decreases die perfonnance tiiat large bandgap. it has higher blocking voltage [31. SiC is tile "''^"=^'^'' ^ ^"gh shon channel effects. Compressing tile most rising substiate for power MOSFETs and odier power ''""' ^ ^ ^ ^ ^ ^ ^ '"to a nanometer MOSFET causes compelhng devices due to its high blocking voltage, gnat operating '='"''™S'» »<• dMiculties wiUl tile contiol of tile short temperamre, and admirable diennal conductivity. 4H-SiC '^^'"^^' effects [6-8]. According to our knowledge of con-
cern, ull now tiiere is no analytical model on hand widiin die tS^n^ Ongo..! conirai li„m ilm work m., 1, us.^ under *e lemu Uleramre for tiic Uireshold voltage and surface potential of a k ^ H l B ot Uie Cnaii.. Conrnions Aimbuiloi, 3.0 lirance Any """"scalc 4H-SiC MOSFET The model presents die
" u e t r r X o l T ^ S ' T S r ' ' " " " " * " " ' ' * ' " ' ' * " J ° ! i ™ " » S = - " » - * > « potential of a nanoscale 4 H - S , C MOSFET usmg Uie two-dimensional (2D) Poisson equation 20434262/1G 025011+WS33.00
© 2016 Vietnam Academy ol Science & Tectinttogy
Adv NaL SCI Nanosci. Nanote<^inot 7 (2016) 025011
Table 1, List of symbols and their descriplion.
Rgure 1. Structure of a 4H-SiC MOSFET.
Symbol L Egsic K VT
£ J : S ,
* M 9 NA N
Nb
"S,
£s, esic
£ox 's, 's,c U
^six) VGS V>ub VDS T
Confession channel length energy band gap of SiC Boltzmann constant the thermal voltage band gap in Si metal gate work function electron charge body doping concentraiion.
source and drain doping concentration substrate concentration intrinsic carrier concentration in
silicon dielectric constant of Si dielectric constant of SiC gate oxide dielectric constant silicon film thickness SiC thin film thickness thickness of gate oxide layer surface potential in thin film gale to source voltage.
the substrate bias drain to source voltage Temperature
Numeiic v a h i e S ' lOOnm K 3.25 eV ^ 1.38 X 1 0 - ^ 4 0.026 V M ; I . l e V S , 4.35 eV M 1.6 X I O - " q ^ 1 X 1 0 " c m ' ^ 2 X 1 0 ^ c m - ' J 1 X 1 0 " cm-^ ^-;
1.45 X lO'^cm^.
11.7 9.7 20 100 nm , yj- 3 0 n m 5 i i m unknown * 0.1 V * OV
0.5 V
3 0 0 K '
[9]. The 2D Poission equation may be solved by using the four boundary condition in the SiC region, and analyzing the behaviour of the threshold voltage [9, 10), surface potenUal.
and electric field witii varying device parameters like gate oxide thickness (/„,), 4H-SiC diin layer tiiickness C/4H-S.C).
channel iengtii (L). and body doping (N^). The intention is to study a physics centered 2D model for a 4H-SiC MOSFET witii the aid of solving the 2D Poisson equation [9]. Note that this model can be utilized as a useful tool for the character- ization and design of high-efficiency 4H-SiC nanoscale MOSFETs together wilh tiie short channel peculiarities by varying various physical parameters. The validity of die mode! is checked by matching die model results widi the 2D simulation results gadiered utilizing T-CAD [ i l , 12]
2. Two-dimensional structure of a 4H-SiC MOSFET The stmcture of die 4H-SiC MOSFET is shown in figure 1.
When compared lo a silicon MOSFET, the 4H-SiC MOSFET stnicture is especially helpful for device scaling. In tiiis stmcture a 4H-SiC epilayer is grown on a silicon substrate.
The epilayer is doped widi die borun concentration of 1x10 ^cm ^^ [9]. The phosphoms concentration of 2 x 1 0 cm I9J is used for source and drain region doping The silicon dioxide layer is mamtained between the gate metal and tiie 4H-SiC layer and tiie tiiickness of tiie gate oxide layer is t„. All die device design parameters witii specific values are tabulated in table 1. The compact model will be used for die characierization and design of high-effi- ciency nanoscale 4H-SiC MOSFETs.
2.1. Surface potential and electric field model Before access of inversion let us write the 2D PoissoQ equation in tiie SiC tiun film of a 4H-SiC MOSFET, f«te,:
sented in iigure 1 as follows (9, 11, 13] '''
forO ^x ^ L,0 ^y ^ ts,c. (1):
The surface potential profile in tiie SiC film will alsote approximated by a parabolic function, as carried out ift [9. II, 13], i.e.
<t>ix, y) = ^s(x) -\- b,ix)y -|- b2ix)y^
fovO^x^L, O^y^tsic. (2) where tiie coefficients biix) and b2(x) are functions of variable x. EquaUon (1) may be solved by using die following fiMT boundary conditions [9, I I , 13]:
(a) At die source side tiie surface potential is
0(0,0) = 05(0) = Vii.s,c. (3)
where 0/r_sic ^^ ^^ Fermi potential in SiC.
fcSo.. Nanosa.Nanoteetmr< 7IP (b) At the diain side the surface potential is
o ( t . 0) = ffljCL) = 14^5^ + v ^ .
(c) Electnc field at die interface of Ihe gate oxide and SiC film is continuous, i.e.
Fd^Ci^l ^ .;„ Usjx) -
L <'y J „ o esicl / „
. (ViLSjc + tr + Vis) - (V„-.s,c -I- <r)e-«- ^ ^ 1 - e - 2 " °
^ ('i..s.c - U r -F V4.s)e-"- - (V„.sic -I- a) 1 - e - 2 "
(d) The electtic field al tile interface of SiC and die sdicon ^'^^ ^ " " * " "^ ""^'"
substrate is
F d ^ C i j O ] ^ esi ( ' K . b - j i U . l s i c ) ' ) L ^y J ^ , „ esicl <s, I
By differentiating equation (12) we obtain the electric field A\s^ - BAe-^- (15) d ^ W .
d i By usmg die boundary conditions (5) and (6), we can
obtain die coefficients i,(x) and biix). Then by substimting diese coefficients mto die expression for tjiix, y) and setting y = 0. we obtain
•Pfe(j:)
di2 *s(i) = A
2.3. Threshokl voltage rttodel
The flireshold voltage model can be obtained by calculating die minima of die surface potential (12). From die condition
" CSK:/
?SiC
'•s\-7r- + — ^
I Q , Csic.) 21U^
(8) we obtain
where CQ^, CSJ and CSK:. are die capacitances per umt area for die gate oxide layer, silicon layer and 4H-SiC film, respectively
C „ = ^ . C „ = ^ a n d C s , c = ^
The solution of equation (7) must satisfy die boundary conditions
MO) = 4>t,.
<t>s{l-) = <t>bi,siC
Let us set A = V Q and ff = 0/a. The second order inhomogeneous differential equation (7) widi a constant coefBcient has die foUowing soludon
OsM = Ae^ -I- Be-^ - a. n21
-24AB -
The threshold vollage is the mmimum value of g«e to source voltage (Vcs) at which a channel is established by die gate oxide at tiie surface of die 4H-SiC MOSFET. Tlierefore, in a 4H-SiC MOSFET, die tiireshold voltage is taken to be diM value of Vcs for which tiie surface potential is equal to twice die difference between die intrinsic and extrinsic Fermi level 0f. J, [9, 10, 12-15]:
= 20^.s (17)
Here 0^ IS die value of die surface potential at which die inversion electron charge density in die 4H-SiC device is die same as die doping concentration. As a consequence, tiie diieshold volt^e is defined as die value of Vcs at which die minimum surface potential 0^^^ is equal to 0^. Hence, accordingly, we wiU assess tiie value of tiie direshold voltage by substimung expression (16) into equation (17) and solving for equation (16) by putting tiie expressions of a, ^ A a A and B
-~K2 + ^ -
Adv NaL So - Nanosci NanolechnoL 7 (2016) 025011 where
K, = b'[4IN-H')- 1], Ki = l>|4(Wi,,sic + M- 1MN) - Itfjl
+ 1ab{'HN-N'^) - I}, AS = a {4(mi,,s,c + M - mm - 20^1
-tttl- 4(M' - MH,,s,c) + nM4(JV - N") - I ) , M I -
o [es,c 's.cES,cL I, 2 e
:s,c-l-CsJ ••'JJ' 1 C,
sicL
2 'sic^sic L 2Csic -f- Cs, J
where A^i, K2, ATj, Af, A^, a, and b are constants and die expressions are as mentioned above and L being the channel length of the device.
Previously Mishra et a/ [16] have reported die analytical modeling of die potential profile of an SOI (sihcon on insu- lator) tunnel FET by solving die 2D Laplace's equation, i.e.
d^0(^.y) d V ( ^ Ax^ d / ^
In tiieir approach die impact of space charge has been neglected because of tiie light doping profile of tiie channel.
However, tiiis work deals widi die 2D Poisson's equation, i.e, 'iMx.y)
Ax^
^H{x, y) dy2
qN^
£sic' widl consideration of die channel doping profile to evaluate tiie potential distribution, and die direshold voltage of tiie 4H- SiC MOSFET. Botii tiie approaches consider die same boundary conditions, except die 4 ± case where diey have calculated die electric flux at die channel and buried oxide interface (refer to equation (7) of [16]) and we have detennined die electnc flux at die channel/substrate interface as diere is an SOI layer (refer to equation (6) of dus work).
3. Results and discussion 3.1. Surface potential
To validate die suggested analytical model, die 2D device simulator T-CAD [17] is used for die simulation of die sur^
face potential distnbuUon widiin tiie SiC layer and die direshold voltage (V^,) variation and die results are compaied widl die analytical model. Figure 2 shows tiie surface potential vanation along die channel Iengtii for distinct values of dram voltages. It is understood from figure 2 tiiat diere is
*^:^
(A )
antlal 4 0.•g 2
Surface p
u-
a slmulaflon
— modeling
v^-asv - -V„s-I.I)V . . - -V„s-LSV
«%»'
tta -I
w 1
lf' 20 40 60 80 _ Channel length (nm) Figure 2. Graph for surface potential versus channel lengtfi for . v' Kos^OSV. Vas=1.0V, Vos=i.5VandVos=2.0V.]TiB. •' device parameters are used as foUows; Vs^b = 0 V. Vc^ = 01V ' NA = 1 X 10" cm-\N=2x 10^°cm~\ls,c^S0,mi.t^ = Sm
Is, = 100 nm and ijiM = 4.35 eV. ^*
0 20 40 €0 80 160 Channel length (nm) Rgure 3. Graph for surface potential versus channel IcngUi for 'ox = 3 nm. r,,, = 6 nm, /Q, = 9 nm. The device parameters are Ui as foUows. V,|,[, = 0 V, Vaj = 0.5 V Vbs = 0 1 V N^=\ X 10"cm-\N = 2 x 10=<'cm-^ (s,c = 30nni, 'si = 100 nm and (^^ = 4.35 eV.
no powerful change in die potential at tiie source side anda very infinitesimal change at die drain side. As a final result Vas has a very small effect on /Q after saturation and it iii visible from die figure tiiat diere is a negligible shift withitt, die factor of die minimum surface potential regardless of % applied drain bias voltage. For diis reason, drain-indue**^' banier lowering is substantially reduced for die 4H-S comparable to silicon. The model results and tiie simul results [16] are correlated widi each odier to prove die ( uracy of our suggested analytical model.
Adv. Mat So NanoscL Nanoteehnol. 7 (2016) (^5011
& 2.0
I
u
ao
20 40 60 80 Channel length (nm)
100
Rgure 4. Graph for surface potential versus channel lengfli for Vos = 0.1 V, VGS = 0.3 V, V^^ = 0.5 V The device parameiers ar^
used as foUows: V^^ = 0\, VDS = 0.5 V. N^ = 1 x 10'•'cm-^
N=2x 10 cm \ f „ = 5nm,fs,c-30mii, fs, = 100 nm and PM — 4.35 eV.
Figure 3 shows tiie surface potential variation along die channel for various values of oxide tiiickness. When tiie gate oxide tiiickness increased, die electric field decreased, perefore, due to tiie fact tiiat die decrement of electnc field impact ionization also reduced, die rate of tiie generation of carriers was low. So. die contioUability of tiie gate over tiie channel potential increases and it is less prominent to SCEs.
Tlierefore, oxide diickness cannot be scaled right down to very small values due to tiie fact diat die results of tunneling via die tiiin oxide and hot-camer end up prominent.
Figure 4 shows die surface potential variation along die channel for various values of gate voltages. It may be observed from die figure tiiat as tiie gate voltage increases, fliere is quite an increment in die height of tiie barrier at tite source side and dram side. Therefore die surface potential increases in tiie channel region, Consequentiy, drain induced bamer lowenng (DIBL) decreases and die immunity to manage die short channel effects (SCEs) is enhanced.
3.2. Electric Held
Figure 5 shows die electric field distribution variation along die channel for distinct values of gate oxide tiiickness. It may be observed from die figure tiiat at tiie drain side, widi an increase in tiie gate oxide value, die electric field substantiaUy reduces. Hence, flie reduction of tiie electnc field experienced by die carriers in tiie channel may be understood because of tiie reduction of the hot-carrier effect.
6.0(M«8
E 4.00^+08 S 2.00e+{l8
W -2.0Oe+O8 • -«.00e+fl8-
D simulation
— modeling
f
J
0 20 40
1-
ft. - ^
— - t m = S n m
• • •lox=8Bn»
60 80 100 Channel length (nm) Rgure 5. Graph for electnc field versus channel lengdi for /„, = 2 nm, for („, = 5 nm, for J^, = 8 nm The device parameters are used as follows: I' ^ = 0 V, V^s = 0.5 V. AO, = 1 x lO'^ cm"^
^^^=2 X 10^cm-^fs,c = 30nm.is,= iOOnmand^i>«-4.35eV.
0 50 100 150 200 Channel length (nm)
Figure 6. The graph for direshold vollage versus channel lengdi for vanous values of N^ The device parameters are used as follows- V™h = 0 V. Vos = 0.5 V. (s,c = 30 nm, is. = 100 nm and 0M = 4 35 eV.
3.3. Threshold voltage
Figure 6 shows die variation of die tiireshold voltage along die channel for distinct doping concentration. As proven within die figure, tiie direshold voltage increases witii improved body dopmg concentration. Hence, die scaling of
die device can go to a fiinher extent widiout any fiirtiier increase in SCEs by increasing die body dopmg concentra- tion. The tiireshold voltage obtained from tile model corre- lates veiy well widl die simulation result.
Figure 7 shows die direshold voltage variation alongside tiie channel for distinct values of gate oxide tiiickness. When die gate oxide diickness is diminished, die threshold voltage can also be diminished which is die requirement for a faster device Therefore, continuous scaling down of die gate oxide duckness offers a rise to faster devices. However, oxide duckness cannot be scaled all die way down to very small values because tunneling via tiie tiiin oxide layer and hot- carrier effects becomes prominent. It is clear diat tiiere is a
Adv NaL SCI.: h4ai>osci NanolechnoL 7 (2016) 025011
£.1-
£-1-
• t0x=3nm- to3(=6nm .. t „ = 9 n m
0 30 60 90 120 150 180 210 Channel length (nm) Rgure 7. Graph for threshold voltage versus channel length for 'os = 3 nm, (o, = 6 nm, f,,, = 9 nm. The device parameters are used as follows: V,„b = OV, I^DS = 0.5V, Vcs = 0.1 V. is,c = 30nm.
fs, = 100 nm and i^M = 4.35 eV.
close match between the analytical outcome and the 2D simulation outcome.
4. Conclusion
Analytical modelling of tiie electric field, surface potential and direshold voltage for a 4H-SiC MOSFET is developed based on die 2D physical model. The influence of quite a lot of device parameters like gate Iengtii scaling, body doping, SiC duckness, gate oxide diickness on tiie electtic field, tiie surface potential, and die direshold voltage are analyzed. The results envisioned by tiie model are compared witii die 2D simulations perfonned by using a commercially available device simulator SentaunisTM. There is a large drop in die direshold voltage witii die decrease in channel lengdi. The use of 4H-SiC matenal instead of silicon increases die device perfonnance regarding reduced short channel effects. The compact model adequately predicts tiie direshold voltage over a gigantic variety of device parameters and can also be
convenientiy used to characterize and design die nanos 4H-SiC MOSFETs widi tiie desired performance.
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