Settings File Reference Manual

(1)

Settings File Reference Manual

Updated for Intel^® Quartus^® Prime Design Suite: 21.4

(2)

MISC_FILE...1080 NUM_PARALLEL_PROCESSORS... 1081 OBJECT_FILE... 1082 OCP_FILE... 1083 PARTIAL_SRAM_OBJECT_FILE... 1084 PIN_FILE... 1085 POWER_INPUT_FILE... 1086 PPF_FILE... 1087 PROGRAMMER_OBJECT_FILE...1088 PROJECT_OUTPUT_DIRECTORY... 1089 PROJECT_USE_SIMPLIFIED_NAMES... 1090 PROMOTE_WARNING_TO_ERROR...1091 QARLOG_FILE... 1092 QAR_FILE... 1093 QIP_FILE... 1094 QSYS_FILE... 1095 QUARTUS_PTF_FILE...1096 QUARTUS_SBD_FILE...1097 QUARTUS_STANDARD_DELAY_FILE...1098 RAW_BINARY_FILE... 1099 READ_OR_WRITE_IN_BYTE_ADDRESS... 1100 REVISION_TYPE... 1101 RTL_SDC_ENTITY_FILE... 1102 RTL_SDC_FILE... 1103 RUN_FULL_COMPILE_ON_DEVICE_CHANGE... 1104 SBI_FILE... 1105 SDC_ENTITY_FILE... 1106 SDC_ENTITY_HELPER_FILE...1107 SDC_FILE... 1108 SDF_OUTPUT_FILE... 1109 SERIAL_BITSTREAM_FILE... 1110 SIGNALTAP_FILE... 1111 SIP_FILE... 1112 SLD_FILE... 1113 SMF_FILE... 1114 SOFTWARE_LIBRARY_FILE...1115 SOPCINFO_FILE... 1116 SOPC_FILE... 1117 SOURCE_TCL_SCRIPT_FILE...1118 SPD_FILE... 1119 SPYGLASS_MISC_FILE... 1120 SPYGLASS_SYSTEMVERILOG_FILE... 1121 SPYGLASS_VERILOG_FILE... 1122 SRAM_OBJECT_FILE...1123 SRECORDS_FILE... 1124 SVF_FILE...1125 SYM_FILE... 1126 SYNTHESIS_ONLY_QIP... 1127 SYSTEMVERILOG_FILE... 1128 TCL_ENTITY_FILE... 1129 TCL_SCRIPT_FILE...1130

22

(23)

TEMPLATE_FILE...1131 TEXT_FILE... 1132 TEXT_FORMAT_REPORT_FILE... 1133 TIMING_ANALYSIS_OUTPUT_FILE... 1134 USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT... 1135 VCD_FILE... 1136 VECTOR_TABLE_OUTPUT_FILE... 1137 VECTOR_TEXT_FILE... 1138 VECTOR_WAVEFORM_FILE... 1139 VERILOG_FILE... 1140 VERILOG_INCLUDE_FILE... 1141 VERILOG_OUTPUT_FILE... 1142 VERILOG_TEST_BENCH_FILE... 1143 VER_COMPATIBLE_DB_DIR... 1144 VHDL_FILE... 1145 VHDL_OUTPUT_FILE... 1146 VHDL_TEST_BENCH_FILE... 1147 VQM_FILE...1148 ZIP_VECTOR_WAVEFORM_FILE... 1149 Retimer Assignments ...1150 HYPER_RETIMER_ADD_PIPELINING... 1150 HYPER_RETIMER_ADD_PIPELINING_GROUP... 1151 HYPER_RETIMER_ENABLE_ADD_PIPELINING... 1152 HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX... 1153 HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR...1154 HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS... 1155 HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS... 1156 HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION... 1157 Retimer Fast Forward Assignments ... 1158 CRITICAL_CHAIN_VIEWER...1158 FLOW_ENABLE_HYPER_RETIMER_FAST_FORWARD...1159 HYPER_RETIMER_FAST_FORWARD_CUT_ALL_CLOCK_TRANSFERS... 1160 HYPER_RETIMER_FAST_FORWARD_ON_HIERARCHY...1161 Signal Tap Assignments ... 1162 CREATE_PARTITION_BOUNDARY_PORTS...1162 ENABLE_LOGIC_ANALYZER_INTERFACE...1163 ENABLE_SIGNALTAP...1164 PRESERVE_FOR_DEBUG... 1165 PRESERVE_FOR_DEBUG_ENABLE...1166 STP_FILE...1167 USE_LOGIC_ANALYZER_INTERFACE_FILE... 1168 USE_SIGNALTAP_FILE... 1169 Simulator Assignments ... 1170 ACTION...1170 ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS...1171 ADD_TO_SIMULATION_OUTPUT_WAVEFORMS... 1172

(24)

EXTERNAL_PIN_CONNECTION... 1178 GLITCH_DETECTION... 1179 GLITCH_INTERVAL...1180 IMMEDIATE_ASSERTION_FAIL_ACTION... 1181 IMMEDIATE_ASSERTION_FAIL_MESSAGE...1182 IMMEDIATE_ASSERTION_PASS_MESSAGE...1183 IMMEDIATE_ASSERTION_STATE... 1184 IMMEDIATE_ASSERTION_TEST_CONDITION...1185 INCREMENTAL_VECTOR_INPUT_SOURCE... 1186 PASSIVE_RESISTOR...1187 SETUP_HOLD_DETECTION... 1188 SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED... 1189 SETUP_HOLD_TIME_VIOLATION_DETECTION... 1190 SIMULATION_BUS_CHANNEL_GROUPING...1191 SIMULATION_COMPARE_SIGNAL... 1192 SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL... 1193 SIMULATION_COVERAGE... 1194 SIMULATION_DEFAULT_VECTOR_COMPARE_TOLERANCE...1195 SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL... 1196 SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL... 1197 SIMULATION_MODE... 1198 SIMULATION_NETLIST_VIEWER...1199 SIMULATION_SIGNAL_COMPARE_TOLERANCE... 1200 SIMULATION_VDB_RESULT_FLUSH... 1201 SIMULATION_VECTOR_COMPARE_BEGIN_TIME... 1202 SIMULATION_VECTOR_COMPARE_END_TIME... 1203 SIMULATION_VECTOR_COMPARE_RULE_FOR_0... 1204 SIMULATION_VECTOR_COMPARE_RULE_FOR_1... 1205 SIMULATION_VECTOR_COMPARE_RULE_FOR_DC...1206 SIMULATION_VECTOR_COMPARE_RULE_FOR_H...1207 SIMULATION_VECTOR_COMPARE_RULE_FOR_L... 1208 SIMULATION_VECTOR_COMPARE_RULE_FOR_U...1209 SIMULATION_VECTOR_COMPARE_RULE_FOR_W... 1210 SIMULATION_VECTOR_COMPARE_RULE_FOR_X...1211 SIMULATION_VECTOR_COMPARE_RULE_FOR_Z...1212 SIM_BEHAVIOR_SIMULATION...1213 SIM_COMPILE_HDL_FILES... 1214 SIM_HDL_TOP_MODULE_NAME... 1215 SIM_OVERWRITE_WAVEFORM_INPUTS...1216 SIM_TAP_REGISTER_D_Q_PORTS...1217 SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE... 1218 SIM_VECTOR_COMPARED_CLOCK_OFFSET... 1219 SIM_VECTOR_COMPARED_CLOCK_PERIOD... 1220 START_TIME... 1221 TRIGGER_EQUATION...1222 TRIGGER_VECTOR_COMPARE_ON_SIGNAL... 1223 USER_MESSAGE...1224 VECTOR_COMPARE_TRIGGER_MODE...1225 VECTOR_INPUT_SOURCE...1226 VECTOR_OUTPUT_DESTINATION... 1227 VECTOR_OUTPUT_FORMAT... 1228

24

(25)

X_ON_VIOLATION_OPTION... 1229

(26)

Intel

^®

Quartus

^®

Prime Pro Edition Settings File Reference Manual

Advanced I/O Timing Assignments BOARD_MODEL_EBD_FAR_END

Specifies the far-end node to be used in the Electronic Board Description (EBD) path description.

Type String

Device Support

• This setting can be used in projects targeting any Intel FPGA device family.

Notes

The value of this assignment is case sensitive.

Syntax

set_instance_assignment -name BOARD_MODEL_EBD_FAR_END -to <to> -entity <entity name> <value>

Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

*Other names and brands may be claimed as the property of others.

ISO 9001:2015 Registered

(27)

BOARD_MODEL_EBD_FILE_NAME

Specifies the Electronic Board Description (EBD) file that contains the path description for an I/O pin.

Type String

Device Support

Notes

This assignment supports wildcards.

Syntax

set_instance_assignment -name BOARD_MODEL_EBD_FILE_NAME -to <to> -entity

(28)

BOARD_MODEL_EBD_SIGNAL_NAME

Specifies the Electronic Board Description (EBD) path description to be used with an I/O pin. You must specify the EBD file name.

Type String

Device Support

Notes

Syntax

set_instance_assignment -name BOARD_MODEL_EBD_SIGNAL_NAME -to <to> -entity

28

(29)

BOARD_MODEL_FAR_C

Specifies, in farads, the board trace model far capacitance.

Type String

Device Support

• Agilex

• Intel^® Arria^® 10

• Intel Cyclone^® 10 GX

• Intel Stratix^® 10 Notes

Syntax

set_instance_assignment -name BOARD_MODEL_FAR_C -to <to> -entity <entity name>

<value>

set_global_assignment -name BOARD_MODEL_FAR_C -section_id <section identifier>

<value>

(30)

BOARD_MODEL_FAR_DIFFERENTIAL_R

Specifies, in ohms, the board trace model far differential resistance.

Type String

Device Support

• Agilex

• Intel Arria 10

• Intel Cyclone 10 GX

• Intel Stratix 10 Notes

Syntax

set_instance_assignment -name BOARD_MODEL_FAR_DIFFERENTIAL_R -to <to> -entity

set_global_assignment -name BOARD_MODEL_FAR_DIFFERENTIAL_R -section_id <section identifier> <value>

30

(31)

BOARD_MODEL_FAR_PULLDOWN_R

Specifies, in ohms, the board trace model far pull-down resistance.

Type String

Device Support

• Agilex

• Intel Arria 10

Syntax

set_instance_assignment -name BOARD_MODEL_FAR_PULLDOWN_R -to <to> -entity

set_global_assignment -name BOARD_MODEL_FAR_PULLDOWN_R -section_id <section identifier> <value>

(32)

BOARD_MODEL_FAR_PULLUP_R

Specifies, in ohms, the board trace model far pull-up resistance.

Type String

Device Support

• Agilex

• Intel Arria 10

Syntax

set_instance_assignment -name BOARD_MODEL_FAR_PULLUP_R -to <to> -entity <entity name> <value>

set_global_assignment -name BOARD_MODEL_FAR_PULLUP_R -section_id <section identifier> <value>

32

(33)

BOARD_MODEL_FAR_SERIES_R

Specifies, in ohms, the board trace model far series resistance.

Type String

Device Support

• Agilex

• Intel Arria 10

Syntax

set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R -to <to> -entity <entity name> <value>

set_global_assignment -name BOARD_MODEL_FAR_SERIES_R -section_id <section identifier> <value>

(34)

BOARD_MODEL_NEAR_C

Specifies, in farads, the board trace model near capacitance.

Type String

Device Support

• Agilex

• Intel Arria 10

Syntax

set_instance_assignment -name BOARD_MODEL_NEAR_C -to <to> -entity <entity name>

<value>

set_global_assignment -name BOARD_MODEL_NEAR_C -section_id <section identifier>

<value>

34

(35)

BOARD_MODEL_NEAR_DIFFERENTIAL_R

Specifies, in ohms, the board trace model near differential resistance.

Type String

Device Support

• Agilex

• Intel Arria 10

Syntax

set_instance_assignment -name BOARD_MODEL_NEAR_DIFFERENTIAL_R -to <to> -entity

set_global_assignment -name BOARD_MODEL_NEAR_DIFFERENTIAL_R -section_id

(36)

BOARD_MODEL_NEAR_PULLDOWN_R

Specifies, in ohms, the board trace model near pull-down resistance.

Type String

Device Support

• Agilex

• Intel Arria 10

Syntax

set_instance_assignment -name BOARD_MODEL_NEAR_PULLDOWN_R -to <to> -entity

set_global_assignment -name BOARD_MODEL_NEAR_PULLDOWN_R -section_id <section identifier> <value>

36

(37)

BOARD_MODEL_NEAR_PULLUP_R

Specifies, in ohms, the board trace model near pull-up resistance.

Type String

Device Support

• Agilex

• Intel Arria 10

Syntax

set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R -to <to> -entity

set_global_assignment -name BOARD_MODEL_NEAR_PULLUP_R -section_id <section identifier> <value>

(38)

BOARD_MODEL_NEAR_SERIES_R

Specifies, in ohms, the board trace model near series resistance.

Type String

Device Support

• Agilex

• Intel Arria 10

Syntax

set_instance_assignment -name BOARD_MODEL_NEAR_SERIES_R -to <to> -entity

set_global_assignment -name BOARD_MODEL_NEAR_SERIES_R -section_id <section identifier> <value>

38

(39)

BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH

Specifies, in farads/inch, the board trace model near transmission line distributed capacitance.

Type String

Device Support

• Agilex

• Intel Arria 10

Syntax

set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH -to <to> - entity <entity name> <value>

set_global_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH -section_id

(40)

BOARD_MODEL_NEAR_TLINE_LENGTH

Specifies, in inches, the board trace model near transmission line length.

Type String

Device Support

• Agilex

• Intel Arria 10

Syntax

set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH -to <to> -entity

set_global_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH -section_id <section identifier> <value>

40

(41)

BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH

Specifies, in henrys/inch, the board trace model near transmission line distributed inductance.

Type String

Device Support

• Agilex

• Intel Arria 10

Syntax

set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH -to <to> - entity <entity name> <value>

set_global_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH -section_id

(42)

BOARD_MODEL_TERMINATION_V

Specifies, in volts, the board trace model termination voltage.

Type String

Device Support

• Agilex

• Intel Arria 10

Syntax

set_instance_assignment -name BOARD_MODEL_TERMINATION_V -to <to> -entity

set_global_assignment -name BOARD_MODEL_TERMINATION_V -section_id <section identifier> <value>

42

(43)

BOARD_MODEL_TLINE_C_PER_LENGTH

Specifies, in farads/inch, the board trace model far transmission line distributed capacitance.

Type String

Device Support

• Agilex

• Intel Arria 10

Syntax

set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH -to <to> -entity

set_global_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH -section_id <section identifier> <value>

(44)

BOARD_MODEL_TLINE_LENGTH

Specifies, in inches, the board trace model far transmission line length.

Type String

Device Support

• Agilex

• Intel Arria 10

Syntax

set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH -to <to> -entity <entity name> <value>

set_global_assignment -name BOARD_MODEL_TLINE_LENGTH -section_id <section identifier> <value>

44

(45)

BOARD_MODEL_TLINE_L_PER_LENGTH

Specifies, in henrys/inch, the board trace model far transmission line distributed inductance.

Type String

Device Support

• Agilex

• Intel Arria 10

Syntax

set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH -to <to> -entity

set_global_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH -section_id <section identifier> <value>

(46)

OUTPUT_IO_TIMING_ENDPOINT

Specifies the node at which output I/O Timing ends.

Type Enumeration Values

• Far End

• Near End Device Support

• Agilex

• Intel Arria 10

Syntax

set_instance_assignment -name OUTPUT_IO_TIMING_ENDPOINT -to <to> -entity

set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT -entity <entity name>

<value>

set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT <value>

Default Value Near End

46

(47)

OUTPUT_IO_TIMING_FAR_END_VMEAS

Specifies, in volts, the measurement voltage at the far-end.

Type String

Device Support

• Agilex

• Intel Arria 10

Syntax

set_instance_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS -to <to> -entity

set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS -section_id <section identifier> <value>

set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS <value>

(48)

OUTPUT_IO_TIMING_NEAR_END_VMEAS

Specifies, in volts, the measurement voltage at the near-end.

Type String

Device Support

• Agilex

• Intel Arria 10

Syntax

set_instance_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS -to <to> -entity

set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS -section_id

set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS <value>

48

(49)

Analysis & Synthesis Assignments ADV_NETLIST_OPT_ALLOWED

Specifies whether the Compiler should perform advanced netlist optimizations, such as gate-level retiming or physical synthesis, on the specified node or entity. If this option is set to 'Default', the Compiler duplicates, moves, or changes the synthesis of the node or entity, or allows register retiming during netlist optimization, only if doing so does not negatively affect the timing or performance of the design. If this option is set to 'Always Allow', the Compiler can alter the node or entity, even if doing so affects the timing or performance of the design. Intel does not recommend using this setting.

If this option is set to 'Never Allow' the Compiler cannot alter the node or entity.

• Always Allow

• Default

• Never Allow Device Support

• Agilex

• Intel Arria 10

This assignment supports synthesis wildcards.

Syntax

set_global_assignment -name ADV_NETLIST_OPT_ALLOWED -entity <entity name>

<value>

set_instance_assignment -name ADV_NETLIST_OPT_ALLOWED -to <to> -entity <entity name> <value>

Example

set_instance_assignment -name adv_netlist_opt_allowed "always allow" -to reg

(50)

ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP

Specifies whether to perform WYSIWYG primitive resynthesis during synthesis. This option uses the setting specified in the Optimization Technique logic option.

Type Boolean

Device Support

• Agilex

• Intel Arria 10

This assignment is included in the Fitter report.

Syntax

set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP <value>

set_instance_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP -to <to> - entity <entity name> <value>

Default Value Off

Example

set_global_assignment -name adv_netlist_opt_synth_wysiwyg_remap on

set_instance_assignment -name adv_netlist_opt_synth_wysiwyg_remap on -to foo

See Also

Optimization Technique

50

(51)

AGGRESSIVE_MUX_AREA_OPTIMIZATION

Performs aggressive area optimization on multiplexers.

• Auto

• Off

• On

Device Support

• Agilex

This assignment is included in the Analysis & Synthesis report.

Syntax

set_global_assignment -name AGGRESSIVE_MUX_AREA_OPTIMIZATION <value>

set_global_assignment -name AGGRESSIVE_MUX_AREA_OPTIMIZATION -entity <entity name> <value>

set_instance_assignment -name AGGRESSIVE_MUX_AREA_OPTIMIZATION -to <to> -entity

Default Value Auto

Example

set_global_assignment -name aggressive_mux_area_optimization off

set_instance_assignment -name aggressive_mux_area_optimization on -to accel

(52)

ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION

Allows the Compiler to infer shift registers of smaller size than the built-in threshold that synthesis uses.

Type Boolean

Device Support

• Agilex

• Intel Arria 10

Syntax

set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION

<value>

set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION - entity <entity name> <value>

set_instance_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION -to

<to> -entity <entity name> <value>

Default Value Off

Example

set_instance_assignment -name allow_any_shift_register_size_for_recognition off -to foo

52

(53)

ALLOW_CHILD_PARTITIONS

Specifies whether or not an instance or a section of design hierarchy can contain user partitions.

Type Boolean

Device Support

Notes

Syntax

set_global_assignment -name ALLOW_CHILD_PARTITIONS -entity <entity name> <value>

set_instance_assignment -name ALLOW_CHILD_PARTITIONS -to <to> -entity <entity name> <value>

Example

set_global_assignment -name allow_child_partitions off

set_instance_assignment -name allow_child_partitions off -to "sub:inst"

(54)

ALLOW_POWER_UP_DONT_CARE

Causes registers that do not have a Power-Up Level logic option setting to power up with a don't care logic level (X). A don't care setting allows the Compiler to change the power-up level of a register to minimize the area of the design.

Type Boolean

Device Support

Notes

Syntax

set_global_assignment -name ALLOW_POWER_UP_DONT_CARE <value>

Default Value On

Example

set_global_assignment -name allow_power_up_dont_care off

See Also Power-Up Level

54

(55)

ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES

Allows the Compiler to take shift registers from different hierarchies of the design and put them in the same RAM.

• Always

• Auto

• Off

Device Support

• Agilex

• Intel Arria 10

Syntax

set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES

<value>

set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES - entity <entity name> <value>

set_instance_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES - to <to> -entity <entity name> <value>

Default Value Auto

Example

set_global_assignment -name allow_shift_register_merging_across_hierarchies off set_instance_assignment -name allow_shift_register_merging_across_hierarchies off -to foo

See Also

Auto Shift Register Replacement

Settings File Reference Manual