Development of a generic digital controller for power electronic applications

CAPE PENINSULA UNIVERSTIY OF TECHNOLOGY Library and Information Dewey No.. Services. .f.!.&~...G.~/:...3...!.2..wJ (JO.

CAPE PENINSULA UNIVERSITY OF TECHNOLOGY. 1111111111111111111111 20115570. '"'::)00.

Cape Peninsula. University of Technology. DEVELOPMENT OF A GENERIC DIGITAL CONTROLLER FOR POWER ELECTRONIC APPLICATIONS. by. CHARLROELOFJOOSTE. Thesis submitted in fulfilment of the requirements for the degree. Master of Technology:. in the Faculty of. Electrical Engineering. ngineering. at the Cape Peninsula University of Technology. Supervisor:. Dr R.H. Wilkinson. Cape Town. April2011. CPUT Copyright Information The dissertation/thesis may not be published either in part (in scholarly, scientific or technical journals), or as a whole (as a monograph), unless permission has been obtained from the university.

Declaration I, Ch3!1 Roelof Jooste,. of this thesis represent. my. own unaided work, and that tbe thesis has not previously been submitted. for. academic. examinations. declare that the contents towards any qualification.. my own opinions and not necessarily. Furthermore,. those of the Cape Peninsula. of Technology.. Signature: C.R. Jooste. 2011/04/15. Date:. Copyright. © 2011. A Il righLH reserved.. Cape Penin. ula University. of T chnology. it represents University.

Abstract Dev.elopment of a Generic Digital Controller for Power Electronic Applications C.R. Jooste Thesis: MTech (Electrical. Engineering). April2011 This thesis presents firmware,. an investigation. involved in power electronic. aim was to determine existing controllers.. converter. the optimal controller Explanations. The design considerations. tools, hardware. and. control and feedback.. The. architecture. As soon as the architecture. controller commenced. provided.. into the genene. through. research of. was established,. design of the. for the various components. selected were. when designing. a printed. circuit board. (PCB) with mixed signals was also presented.. The theory behind the control. of a rnulticcll convcrter as well. implementation. 3.<;. the practical. scheme in firmware was presented.. 11. of the control.

Acknow ledgements I would like to express my sincere gratitude to the following people and organisations: My family and friends for their continued support and motivation. My supervisor, Dr Richardt Wilkinson, for his guidance and support. The Centre for Instrumentation. Research (CIR) staff, store members and. students. Special thanks to my colleagues Jason Quibell and Rory Pentz. The financial assistance of the National Research Foundation,. Cape Penin-. sula University of Technology and F'SATI towards this research is acknowledged.. Opinions expressed in this thesis and the conclusions arrived at, arc. those of the author, and are not necessarily to be attributed mentioned establishments.. Hl. to the respective.

Contents. Declaration Abstract. n. Acknow ledgements. iii. Contents. IV. vn. List of Figures List of Tables. x. xu. Nomenclature 1. 2. 3. 1. Introduet ion Introduction. 1.2. Project. Background.. 6. 1.3. Project. Objectives. 9. 1.4. Thesis Outline .... 10. Digital Control Systems. 12. 2.1. Introduction. 12. 2.2. Digital Control. 2.3. Key Components. 2.4. Research ill the Area of Digital Controllers. 18. 2.5. Advantages. and Disadvantages. 24. 2.6. Conclusion. . . . . . . . . . . . . . . . .. Controller 3.1. to Digital Control in Power Electronics.. 1. 1.1. ... 12 of a Digital Controller of Digital Control Systems. Design and Considerations. 14. 26. 27 27. Introduction........ IV.

CONTENTS. v. 3.2. Controller. Specifications. 27. 3.3. Controller. Overview. 28. 3.4. Controller. Components.. 3.5. CIRPEC. 3.6. Power Supply, Reset Circuitry. 3.7. PCB Design and Considerations. 55. 3.8. Conclusion............. 60. Features. ... 29 49. .... and Considerations. 4 Firmware Development 4.1- Introductiou. 61. . . . . .. 61. Modulation. 61. 4.2. Pulse-width. 4.3. Firmware. 4.4. Booting the DSP. 78. 4.5. Conclusion.. 79. Modules. 67. 5 Results. 81. 5.1 Introduction. 6. 51. .. 81. 5.2. Experimental. Setup .. 81. 5.3. Experimental. Results.. 84. 5.4. Conclusion.. 100. Conclusion. 103. 0.1 Introduction. .. 103. 6.2. Ilardwarc. 103. 6.3. Firmware. 104. 6.1. Thesis Contribution.. 105. G.5. Future Work.. 105. List of References. 107. A Schematics. 115. A.l. CIRPEC. Schematics. B Printed Circuit Boards B.l. CIRPEC. Printed. 13.2. CIn.PEC. Photos. Circuit Boards. ... C Datasheet Information. 115 132 132 143 145.

CONTENTS. C.1. DSP .. D MATLAB. vi 14.5 148.

List of Figures 1.1. J(. basic block diagram of a switching power converter.. 2. 1.2. Inclusion of the controller block. . . . . . . . . . . . . .. 3. 1.3. Converter power loss vs. efficiency. (Erickson fj Maksimovic, 2004). 4. 1.4. System overview diagram.. 6. 1.5. The multi cell inverter topology.. 2.1. Switching converter and controller block. . . . . . .. 13. 2.2. Digital PWM controller.. 13. 2.3. Block diagram of the analog-to-digital. . . .. 7. (Maksimovic ct al., 2004) conversion process.. (Luo. ei al., 2005) . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... 15. 2.4. Black diagram of a digital-to-analog. 18. 3.1. Black uiagram of the CIRPEC.. . . . . . . . . . .. 29. 3.2. JTAG header interface to DSP.. . . . . . . . . . .. 35. 3.3. Connections for the EPCS4 configuration device.. 37. 3.4. GPIO pins selected for Flash memory address pins.. 44. 3.5. EEPROM configuration byte.. . . . . . . . . . . . .. 46. 3.G. Off-board connector.. . . . . . . . . . . . . . . . . .. 48. 3.7. Graphical representation. 3.8. Reset circuitry of the CIRPEC.. . . . . . . . . . . . . . . . .. 54. 3.9. Current return paths. . . . . . . . . . . . . . . . . . . . . . .. 58. converter.. (Luo et al., 2005). of the CIRPEC power distribution.. 53. 3.10 Deccupling Vee/Gnu pairs around the DSP (left) and FPGA (right).. 59. 4.1. Interleaved switching. 62. 4.2. Rcsul ting switching function.. 64. 4.3. Single-cell multiccll converter.. 64. 4.4. p-cell multiccll converter. . . .. 65. 4.5. Interleaved switching waveforms for a five-cell converter.. 66. .. vii.

LIST OF FIGURES 4.6. VUl. A subplot of the interleaved switching method and resulting switching function waveforms for a five-cell multicell converter.. 67. 4.7. Total switching [unction of a five-cell multiccll converter.. 68. 4.8. DSP flow chart. 71. 4.9. Basic blocks necessary to generate PWM.. .. 4.10 Triangle positive and negative cycle. 4.11 Dual-port. RAM block implemented. 73. 74. . .. on FPGA ... 76. 4.12 PWM blocks required for a single-cell.. 77. 4.13 Dead time implementation.. 77. 5.1. Experimental. 82. 5.2. Resulting. 5.3. PWM gating signal generated. 5.4. PWM gating and complementary. setup.. PWM of a single gating signal.. single-cell firmware module.. 85. by the single-cell firmware module. gating signal generated. 85. by the. . . . . . . . . . . .. 86. ·1).5. Measured. FFT of a single PWM gating signal. .. 87. 5.6. Measured. dead time.. 88. 5.7. Switching [unction o[ a two-cell simulated. 5.8. Two-cell multicell inverter firmware PWM as output analyser.. 5.9. . . . . . . . . . . . . . . . in MATLAB®.. .. 90. by the logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... PWM gating and complementary. gating signals generated. 90. by the. two-cell firmware module.. 91. 5.10 Total switching function of the two-cell.. 91. 5.11 Swi telling function of a thr-ec-cell multicell inverter.. 93. G.12 ThH~e-cell multiccll inverter firmware PWM gating signals.. 93. 5.13 PWM gating and complementary. gating signals generated. by the. thTec-cell firmware module. . . . . . . . . . . . . . . . . . . . . .. 5.14 Simulated. switching. (unctions [or the five-cell multicell converter.. 94 96. 5.15 Five-cell rnult.iccll inverter firmware PWM gating signals. . . . ... 96. 5.16 Five-cell firmware PWM gating and complementary. 97. 5.17 Total switching 5.18 Unfiltered verter.. output. gating signals.. function for a five-cell rnulticcll inverter. voltage measured. . . . ... from the five-cell mult.icell in-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... 5.19 Filtered output voltage measured 5.20 First sine table.. . .. ;).21 Second sine table ... 98. from the five-cell multicelI inverter.. 98 99 100 101.

ix. LIST OF FIGURES 5.22 Third sine table.. 101. 13.1 CIRPEC. top layer.. 133. B.2. CIRPEC. bottom. 134. B.3. CIRPEC. ground plane ... 135. 13.4 CIRPEC. power layer. ... 136. B.5. CIRPEC. LOpsilkscreen overlay.. 137. B.6. CrR.PEC bottom. B.7. CIRPEC. top sokier mask.. B.8. CIRPEC. bottom. B.9. 3D representation. layer.. B.ll. solder mask.. 140. . . .. of the top side of the CIRPEC. as generated. by. . . . . . . . . . . . . . . . . . . ... of the bottom. side of the CIRPEC. 141. as generated. by the Altiurn Designer software.. 142. Top side of the CIRPEC.. .. 143. . . . . .. 144. DSP block diagram. 146. B.12 Bottom side of CIRPEC. C.l. 139. ...... the Altiurn Designer software. B.10 3D representation. 138. silkscreen overlay.. TMS320C6720.

List of Tables 1.1. Basic functions of switching converters.. . . . . .. 2. l.2. Types of switched-mode. devices.. 5. 2.1. Types of ADCs (Luo et al., 2005). 2.2. Comparison. semiconductor. of current. Van Heerden (2003).. digital. .. controllers.. 17. Table adapted. . . . . . . . . . . . . . . . . .. 2.3. Comparison. 2.4. Features. of the EVMs used by Liu (2005).. 2.5. Features. of the EVM used hy Predie et al. (2001) ... 2.6. Advantages. 2.7. Disadvantages. 3.1. Controller. 3.2. DSP features.. 3.3. Components. 3.4. Boot options supported. 3. r.U. of current digital controllers. specifications.. AD. . ..... 24 25 25. . . . . . . . . . . . . . . .. 31. (2006a). 32. for the C6720.. 32. of the C9230CIOO ROM. Texas Instruments by the on-chip bootleader pins.. . . . . . . . . . . . . . . . .. connector pin description.. device features.. .. 3.13 SDRA M features.. .. 35 37 3. (Texas Instruments,. word (Samsung. 3.14 Flash meuiory features.. Electronics,. 1998). 40. .. 41. .. 42 43. 2008). (Spansion Inc., 2007). x. Digital 34. . register.. 33. .. 3.11 TLV.1638 features. configuratiou. (Spectrum. device features.. features. 3.10 ADC configuration 3.12 DA. 23. 28. :t8 Serial configuration 3.9. 20. . . . . . . . . .. l d-pin emulator. EPIC12. continued.. of digital control systems.. Inc., 20(7) 3.7. 19. of digital control systems.. Boot Illode selection for jumper. 3.G DSP. from. .. 43.

LIST OF TABLES. Xl. 3.15 Serial EEPROM. features.. (Microchip Technology,. 3.16 USB device features.. (ST-NXP Wireless, 2006). 3.17 Clock driver features.. Texas Instruments. 3.18 Fibre optic features.. (Avago Technologies,. 3.19 CIRPEC. features... 5.1. Measurement. 45. .. 46. (2005 a). 4_ 7. 2006) .. 49. . . . . . . . . . . . . . . . . .. 50. 3.20 Voltage and current requirements 3.21 Voltage regulators. 2007). of CIRPEC. on the CIRPEC.. equipment.. . . . . . .. components. in rnA.. 52 52 84.

Nomenclature Abbreviations ac. Alternating. Current. ADC. Analog-to-Digital. AIC. Analog Interface Controller. ASIC. Application-Specific. CAD. Computer. CAS. Column Address Strobe. CCS. Code Composer. CIR. Centre for Instrumentation. CIRPEC. CIR Power Electronics. CMOS. Complementary. CSV. Comma Separated. CPES. Centre for Power Electronics. CPU. Central Processing. DAC. Digi tal- to- Analog Converter. dc. Direct Current. DMA. Direct Memory Ac ess. dMAX. Dual Data Movement Accelerator. DP. Dou ble- Precision. DPWM. Digi tal Pulse- Width Modulator. DSP. Digi Lal Signal Processor. EEPROM. Electrically. EMI. Electromagnetic. EMIF. External. Converter. IC. Aided Design. Studio Research. Controller. Metal Oxide Semiconductor Values Systems. Unit. Erasable. Programmable. Interference. Memory Interface. xii. ROM.

NOMENCLATURE. Xlll. ENOB. Effective Number of Bits. ER. Effective Resolution. EVM. Evaluation Module. FFT. Fast Fourier Transform. FIFO. First In First Out. FPGA. Field Programmable Gate Array. FSR. Full-Scale Range. GPIO. General Purpose Input Output. GTO. Gate- Turn-Off Thyristor. I2CjI2C. Inter-Integrated Circuit. IC. Integrated Circuit. lCM. Imbricated Cells Multilevel. IDE. Integrated Development Environment. IGBT. Insulated Gate Bipolar Transistor. lP. Intellectual Property. JTAG. Joint Test Action Group. LDO. Low Dropout. LVCMOS. Low-Voltage CMOS. LVDS. Low-Voltage Differential Signalling. LVTTL. Low-Voltage Transistor-Transistor. McASP. Multichannel Audio Serial Port. MFLOPS. Million Floating Operations Per Second. MIPS. Million Instructions Per Second. MMACS. Million Multiply-Accumulates. MOSFET. Metal Oxide Semiconductor Field Effect Transistor. PCB. Printed Circui L Board. PEC. Power Electronics Controller. PEG. Power Electronics Group. PLD. Programmable Logic Device. PLL. Phase-Lock Loop. PQFP. Plastic Quad Flat Pack. Logic. Per Second.

NOMENCLATURE. XIV. PWM. Pulse-Width. Modulation. RAM. Random Access Memory. RAS. Row Address Strobe. ROM. Read Only Memory. RSDS. Reduced Swing Differential. SIH. Sample-and- Hold. SAR. Successive Approximation. SDRAM. Synchronous. SIMO. Slave In Master Out. SINAD. Signal-to-(Noise. SNR. Signal-to-Noise. SOIC. Small Outline IC. SOMI. Slave Out Master In. SP. Single- Precision. SPI. Serial Peripheral. SQNR. Signal- to-Quantization-. SHAM. Static Random. SSTL. Stub Series Terminated. THD. Total Harmonic. TI. Texas Instruments. TQFP. Thin Quad Flat Pack. TSOP. Thin Small Outline Package. TSSOP. Thin-Shrink. TTL. Transistor- Transistor. USB. Universal Serial Bus. + Distortion) Ratio. Interface Noise Ratio. Access Memory Logic. Distortion. Small Outline Package. 3.141592654. Symbols CJ. Register. Dynamic RAM. Constants 1f=. Signalling. Filter capacitor. Logic.

xv. NOMENCLATURE. d. Duty cycle. de. Duty-cycle. e'l. Quantization. fclk. FPGA clock frequency. fr. Reference frequency. I.,;. Swi tching frequency. Fs. Sampling frequency. 2[,. Current. Lf. Filter inductor. s. Switching function. St. Total switching function. tmnll. Conversion time. t;. Sampling period. Ve,. ith cell capacitor. Vdc. cle voltage. Va. Voltage out. Vref. Reference voltage. Vs. Filtered. Zload. Load impedance. command error. through. the inductor. voltage. output voltage.

Chapter 1 Introduction 1.1. Introduction to Digital Control in Power Electronics. Power electronics electronic. can be said to be the processing. devices, where emphasis. of electrical. power using. is placed on the control of energy flow. (Krein, 1998). It also deals with the efficient processing and control of electric power in applications. ranging from sub-watt. in battery-operated watts for computer variable-speed. portable. equipment. de-de power management. and thousands. of. and office power supplies, to kilowatts and megawatts. for. drives and 1,000 megawatt. to tens, hundreds. devices. inverters. and rectifiers used in the. utility power system. An important controlled. clement of power electronics. power electronics is the switching. awl more specifically. converter.. is a power electronics circuit consisting of semiconductor vert an input voltage' to a voltage of another implemented. by swi tching converters. Maksimovic,. 2004; Mohall et al., 2003).. Figure l.I is an illustration of input power and output. Figure 1.2 illustrates processing. A switching converter 'switches'. which con-. level. Basic functions. that are. are included in Table 1.1: (Erickson. output. fj. of a basic swi tching converter block. IL consists. power ports as well as a control input port.. raw input power is processed the required conditioned. digitally. by the control input specifications. The. to produce. power.. the inclusion of a controller hlock into the basic power. block of a switching power converter.. 1. Control is necessary. to pro-.

2. CHAPTER 1. INTRODUCTION. Table 1.1: Basic functions of switching converters.. Basic functions of switching converters de-de conversion. ac-de rectifier de-ac inversion ac-ac cycloconversion. Direct current (dc) input voltage is converted to de output voltage possibly of smaller or larger magnitude and potentially opposite polarity or reference isolation between input and output grounds Alternating current (ac) input voltage is rectified to give a de output voltage Transformation of a de input voltage into an ac output voltage of controllable magnitude and frequency Couverts au iuput ac voltage into an ac output voltage of controllable magnitude and frequency. Power Input. Switching Converter. Power Output. Control Input Figure 1.1: A basic block diagram of a switching power converter..

CHAPTER. 3. 1. INTRODUCTION. Switching Converter. Power Input. Power Output. Control Input. Feedforward. Feedback. Controller. Figure 1.2: Inclusion of the controller block.. vide a well conditioned variations. and well regulated. output voltage where there may be. in the input voltage or load current.. Switching electrouics. converters. are being implemented. as these high-frequency. switching. in more branches converters. of power. can transfer. in high power density and efficiency. They operate in the discrete-time. energy domain. since the energy and power delivery from the source to the load are no longer in the continuous-time applied.. mode.. Digital control methods. therefore. need to be. (Luo ct al., 2005). Digital control of switching power low-frequency frequency applications. converters. applications (Prodic. is hecoming very common in high-. as well as in low-to-medium. et al., 2003).. High efficiency is desirable in power electronic of converter. systems.. The implications. design with low efficiency, especially in high-power applications,. is evident from the subsequent a converter. power high-. equations.. The power-transfer. can be derived from the following equation:. efficiency (TI) of. (Erickson. fj Maksi-. movie, 2001; Luo el al., 2005) Pout. rJ= --. Pin. where. Pout. is the output power and Pm the input power.. (1.1.1).

CHAPTER. 1. INTRODUCTION. 4. The power loss in a converter can be calculated. by equation. (1.1.2) and is. plotted in Figure 1.3: (1.1.2). Converter. Power Loss vs. Efficiency. 0.9 0.8 0.7. Ê. 0.6. »,. u. c 0.5 ID ·u :E w 0.4. 0.3 0.2 0.1 0 0.25. 0. 0.5. 0.75. 1.25. 1.5. PIassIP out (W). Figure 1.3: Converter power loss vs. efficiency. (Erickson fj Maksimovic, 2004). From equations. (1.1.1) and (1.1.2) and analysing Figure 1.3 it can be deter-. tuined L1Jata converter wi th au efficiency of 50% will have a of its Poul. The power that is lost is inevitably require large and expensive cooling methods and loss. Operaling and reliability. a converter. equal to that. conver ted into heat which may depending. at high temperatures. on the output. power. will lead to instability. issues.. However, if the converter of the output. Plo88. is 90% efficient then the loss power is only 11%. power as calculated. of one represents. 100% efficiency.. in equation. (1.l.3);. while considering. an ry.

CHAPTER 1. INTRODUCTION. Ploss. =. PauL . (~. Ross. =. o.ii. e:. . ... 5. Pzuss PauL. -. 1) =. P out. .. (0 19 - 1). = 11 i01 .. Low power loss enables. (1.1.3). 10. the converter. components. to be more densely. packed allowing for a smaller and lighter converter with minimal temperature rise. In order to achieve this efficiency, switched-mode are operated. as 'switches'.. semiconductor. These power semiconductor. devices. devices are listed in. Table 1.2 (Luo et al., 2005; Mohall et al., 2003). Table 1.2: Types of switched-mode semiconductor devices.. Device GTOs BJTs TGBTs MCTs MOSFETs. Gate- Turn-OIT Thyristors Bipolar Junction Transistors Insulated Gate Bipolar Transistors MOS-Controlled Thyristors MOS Field Effect Transistors. By actively controlling regulate state,. operating. through. The power dissipated. of power converters the multicef. The majority. operates. in the 'off' When. by these devices is therefore very low. power converters. where these switching full-bridge. devices are used in-. and multilevel. topolo-. converter.. of this introductory. references of Erickson. it is possible to. state, its voltage drop is small and so is its. clude huck, boost, buck-boost, half-bridge, gies including. Slow Medium Medium Medium Fast. it is zero and so is the power dissipation.. and well sui Led [or high-efficiency Examples. High Medium Medium Medium Low. When the semiconductor. in the 'on ' (saturated). power dissipation.. Switching Speed. the on/afr states of these 'switches'. tho input or output.. the current. Power Capability. section research was sourced from the. f1 Maksimovic (2004); Maksimovic et al. (2004).

6. CHAPTER 1. INTRODUCTION. 1.2. Project Background. In the last few years much research. in the area of multicell. been conducted. at the Cape Peninsula. Instrumentation. Research (CIR) laboratory.. a need for a digital. Call. University. of Technology's. IL was established. for power electronic. neers and students applications. applications.. with a hardware. this can be a time consuming application. Centre for. that there was. of a generic digital. The controller. platform. exercise.. will provide engi-. to implement. without having to design their own application. been developed. has. troller to provide the necessary control signals.. The focus of this thesis is the design and development controller. converters. power electronic specific board, as. A few firmware modules. that will greatly reduce the time taken to produce. have also working. specific code.. CONTROLLER. 11 11 INVERliER. de POWER. TRANSDUCER. Figure 1.4: System overview diagram.. Figure 1.2 illustrat. s the system overview for the primary. application.. de voltage source is conver ted Lo ac by means of a multi cell inverter. reference to an illverter specifically implies that the converter. A The. will be used for.

7. CHAPTER. 1. INTRODUCTION. de to ac inversion. interchangeably. The terms converter. in this text depending. A controller. is required. and inverter. may therefore. be used. on the context of its appearance.. La generate. the digital pulse-width. modulation. (PWM) control signals. From there the stepped sinusoidal output signal from the inverter is filtered to produce a conditioned conditioned load.. sinusoidal output. Applications. sinusoidal output voltage. The. signal is used to drive an ultrasonic. for the mentioned. system include, amongst. transducer. others, ultra-. sortie welding and drilling. It encompasses. the. and also the firmware development. in-. The focus of this research is purely on the controller. controller. design and implementation. volved in the generation. of the PWM signals that are necessary for control of. the multi cell inverter.. 1.2.1. Multicell Topology. Although. the purpose of this thesis is not the development. verter, understanding primary. application. is required. of the operation. is the control. thereof.. of a multicelI con-. of this topology. since the. An overview of the topology. is. therefore covered in this section. The control signals required and their implementation. will be covered in Chapter. Cs. V"". I I I I I. B!. CeliS. Cell4. Cell3. SSt. s,. SJ!. c. s••. S"". CJ. S3b. 4. Cell2. S". C2. S,.. Cell1. S". C,. S,.. I. =1. +. I I I Vo I I I. Vs. il. I. 1=. Figure 1.5: The multicell inverter topology.. The rnulticoll convcrter topology is also referred to as the "flying-capacitor multilevel. topology",. "nested cells multilevel. topology". or "imbricated. cells.

CHAPTER. 1. INTRODUCTION. multilevel topology" 1999; Wilkinson,. (lCM) (Meynard. 2004; Hansmann,. for many applications directional. 8. Cj. Foch, 1995; Wilkinson,. 1997; Walker,. 2004). The multicelI topology can be used. including de-de, de-ac and also ac-ac converters for uni-. and bidirectional. power flow (Walker, 1999). To re-emphasise,. the. multicell converter will often be referred to as an inverter in this thesis implying it will be used for de-ac inversion. In this topology semiconductor top and bottom capacitors. switches are connected. switches are connected. in series and the. by floating capacitors.. The floating. act as de voltage sources which need to be charged to a particular. voltage in order for the switching. devices not to be destroyed. (Wilkinson,. 2004). This topology can be seen as multiple generic cells made up of a halfbridge configuration. and a capacitor across the input bus. Figure 1.5 illustrates. a five-cell multicelI inverter with each cell being demarcated. A single cell consists of two switching complementary. pair.. devices forming what is called a. When the top switch is conducting,. the bottom. If both of the switching devices are conducting. must be blocking.. time it will cause a short circuit which could have destructive ensure that only one switching. device in a complementary. at the same. implications.. To. pair is conducting. at anyone. instant,. conducting. switch Lo enter the 'off' state before the other switch begins con-. ducting.. Although. is prudent. a period of dead time is inserted.. switch. the rise and fall times of a switching. Lo allow the switch that is transitioning. 'off' state to switch off completely conducting.. Dead time allows the device may differ, it. from the 'on' state to the. before allowing the other device to start. This is clue Lo the fact that the conducting. device takes a period. of time, TJ, before it stops conducting. Typically the rise Lime, TT) is shorter than the fall Lime, TJ, and if switched simultaneously the one switch may still be transitiening. to the 'off' state while the other switch starts conducting.. The ideal voltage across a cell capacitor expressed. as follows: (Hamma lrc. vI. Where Ve. represents. •. =. under balanced. et ol., 1995; Meynard i .Vdc for i = 1, ... ,p p. where prepresenLs. (1.2.1). the 'ith cell capact tor voltage, Vde represents. cells have a voltage-drop the number. can be. et al., 1997). voltage and i the index for the number of cells up La the Commutation. conditions. pth. the input. cell,. across the switching devices of ~p. of cells. The cells are overlapped. to form an.

9. CHAPTER 1. INTRODUCTION. inverter leg capable of switching the input voltage Vdc. The number of cells i. e. p can be increased. depending. on the blocking voltage required.. voltage ripple has an amplitude times the switching frequency,. of. The apparent. Vdc.. p. i; which. filter size by a factor of p2. (Meynard. fj. The output. switching frequency is p. results in a reduction. in the output. Foch, 1995; Molepo, 2003; Wilkinson,. 2004) The multi cell converter relies on the phase-shift trol signals in order to operate. correctly.. control signals needs to be. 211".. ics centred at multiples. 1s and. of. p. and duty cycle of the con-. The phase-shift. between successive. This also results in the cancellation up to and including. (p - 1). -I,. of harmon(Wilkinson,. 2004). The phase-shift. between control signals of successive cells can be expressed. as follows: (Wilkinson,. 2004) <P. = 27r. (1.2.2). p. and the phase-shift as follows: (Wilkinsou,. of the control signal for a single cell can be expressed 2004) <Pi =. (i - 1) . <P for i = 1, ... ,p. Where i is an index for the cells up to the. 1.3. pth. (1.2.3). cell.. Project Objectives. The objectives. of the project include:. • An investigation. into the generic tools, hardware. in power electronic optimal controller. and firmware, involved. control and feedback is required architecture. to determine. the. necessary [or a generic power electronics. controller. A thorough investigation be performed. of controllers designed at other institutions. in order to determine. the applications. the hardware. firmware may have been designed for and from that establish controller. architecture. • Prom this investigation, of a generic controller. will and. a generic. . the trade-olfs that exist as a result of the design rather. than a controller. designed. for a specific.

10. CHAPTER 1. INTRODUCTION. power electronics. application. include time to development • The design and development. will be established.. These trade-offs may. and cost factors. of a generic high-performance. controller for. various power electronic applications.. In order to establish whether the hardware be used to control a multi cell inverter.. functions. as desired, it will. Development. of the multicell. inverter falls outside of the scope of this project, therefore,. the controller. will be tested on a multicell inverter developed in-house. • The development controller,. of various firmware modules to be implemented. this will include a multicell inverter. application.. Other modules. three-phase. on the. module as the primary. may include a half-bridge,. full-bridge. and. motor control module.. In order to determine whether the firmware functions as desired it will be implemented. on the hardware controller mentioned. in the previous point.. Since the rnulticell inverter module is an advanced form of the half- and full-bridge modules, as presented in Chapter 4, only the multi cell inverter module will be testen with a multi cell inverter. fundions. If the multicelI module. as desired it is safe to assume the half- and full-bridge modules. will function as desired. The project. objectives • The development • Feedback. do not include:. of a multicell inverter. from the multicell. inverter,. into the design of the hardware. although. this was incorporated. and a basic firmware implementation. was carried out.. 1.4. Thesis Outline. • Chapter 2 focuses on researching mining the key components. the controller. that are necessary. • Chapter 3 focuses ou the controller. design.. architecture. and deter-. [or control, The controller. specifica-. tions. and the printed circuit board (PCB) design and considerations presented.. are.

CHAPTER. 1. INTRODUCTION. • Chapter 4 focuses. 011. the firmware development.. as well as the interleaved • Chapter. 11. switching method. 5 focuses on the simulation. hard ware and firmware'. • The thesis is concluded in Chapter 6.. The various modules. are presented.. and results. obtained. from the.

Chapter 2 Digital Control Systems 2.1. Introduction. Digital controllers. and digital control methods. come widespread.. They are especially useful in applications. control and monitoring. in power electronics. have be-. requiring complex. such as motor drives and three-phase. power convert-. ers. Digital controllers may include processors such as the microprocessor,. pro-. grammable. and. logic devices (PLD), field programmable. digital signal processors processing. power and decreasing. power electronics. 2.2. (DSP). Technical advantages. at relatively. coupled with increasing. cost have made digital control popular. et. high power levels (Maksimovic. in. ol., 2004).. Digital Control. In order to establish vcstigation. the components. necessary. the controlled. at the output and compensating of the desired output. age despite disturbances. 2.1, is presented. an in-. The objective (Kaye. the signal so that it is within an error margin. Control il:>necessary Lo achieve a desirable output which could be introduced process. fj. the output of the converter by sensing. circuit element values (Erickson. The basic control. is required.. system safely and optimally. Smith, 1989). This is done by regulating. or converter. for a digital controller. into the control of switching converters. of control is to operate. figure. gate arrays (FPGA). fj. again for quick reference.. 12. in the load, input voltage. Maksimovic,. block of a switching. volt-. 2004).. converter, A controller. illustrated. in. is needed to.

CHAPTER. 2. DIGITAL. CONTROL SYSTEMS. 13. Switching Converter. Power Input. Power Output. Control Input. Feedforward. Feedback. Controller. Figure 2.1: Switching converter and controller block.. provide the control input signals to the switching converter any feedback or feed-forward An example consists of. all. and make adjustments. of a digital controller. analog-to-digital. to the control signals.. block is illustrated. converter. as well as process It. in Figure 2.2.. (ADC), a discrete-time. compensator. and a digital PWM gate signal generator. g1 g2. Switching Converter. Va. I. Digital PWM. dc[n]. Discrete-time compensator dc{n] = dc{n-1] + a-e[n] + /).e[n-1] + c-e[n-2]. e[n]. ~. r. -. ADC. +. v.; Figure 2.2: Digital PWM controller. (Maksimovic et al., 2004). An ADC samples the difference between the sensed output voltage, Vo, and the reference' voltage, V,-ef, providing the digital error signal,. c.. The duty-cycle.

14. CHAPTER. 2. DIGITAL CONTROL SYSTEMS. dc, is then determined. command,. by a discrete-time. compensator. the received digital value from the ADC and computing algorithm generate. on the DSP. A digital pulse-width the output. that with the control. modulator. (DPWM). by de.. The control input signals can either be. back into analog signals using a digital-to-analog. or the digital signals can be used for the gating signals, switching. devices.. In this system the DPWM. frequency DPWM can be constructed comparator.. is used to. gating signals at the desired switching frequency as well. as duty cycle as determined converted. by applying. (Maksimovic. converter. (DAC). 91 and 92, of the. serves as the DAC. A high-. using a fast clocked counter and a digital. et al., 2004). In order to achieve fast dynamic response the ADC must sample at least at the same rate as the switching frequency.. The ADC resolution. to be high enough in order to achieve good voltage regulation. also needs. requirements.. el ol., 2004). (Maksimovic. The discrete-time. compensation. de[nJ. +a. =. dc[n - IJ. function of. . e[nJ. + b·. ern - IJ. + c·. ern - 2J. (2.2.1). that runs on the DSP is that of a digital filter. ern], e[n - 1], e[n - 2J represent consecutive compensator's. samples of e. The coefficients a, b, and c are what determine frequency response.. in a fraction of the switching. This computation. the. will need to be computed. frequency such that de can be updated. without. much delay. For this filter it can be seen that there are three multiplications and 3 additions. the greater design.. 2.3. DSPs arc capable of performing. the processing. (Maksimovic. needs the greater. such calculations,. however. the cost and complexity. of the. et ol., 2004). Key Components of a Digital Controller. From the general controller. block illustrated. that there are three key components digital controller.. in Figure 2.2 it was determined. that define the general architecture. of a. These include the ADC, the DSP and lastly the DAC. In. this section a brief overview of these components. is given..

CHAPTER. 2. DIGITAL. Analog signal. CONTROL SYSTEMS. S/H. ,... 15. Quantization & Digitization. Digital codes. Figure 2.3: Block diagram of the analog-to-digital conversion process. (Luo et al., 2005). 2.3.1. The Analog-to-Digital Converter. An ADC is necessary to convert real-world signals from the analog (continuoustime) domain to the digital (discrete-time) digital controller. Important time. tconv. and quantization. domain ready for processing by a. factors when selecting an ADC include conversion error eq. Figure 2.3.1 shows the conversion process. from analog to digital. Firstly,. the analog signal is sampled.. Sampling occurs at regular time. intervals also known as the sampling period T'; The sample-and-hold. (SIR). process samples the analog signal at each interval and holds that value until the next sample interval arrives. A phenomenon known as aliasing can occur if the analog signal is not sampled fast enough. This is a result of important information. being lost or not sampled due to the slow sampling rate.. sampling frequency,. The. F.., should be selected to be at least twice the frequency. of the highest frequency component of the analog signal to be able to exactly recover the analog signal from the sample values. This is referred to as the Shannon sampling theorem or the Nyquisl rule (Proakis & Manolakis, 1996:29) (Tan, 2008:19). Quantization. and digitization of the signal takes place next. Once the signal. has been acquired by the sampler and held, the converter assigns a quantization level that approximates code.. the signal as closely as possible in the form of a binary. Where N bits are used, 2N possibilities. converter.. can be represented. by the. The more bits, the more closely the digital signal will correspond. to the analog signal. The gap between the levels is known as the quantization step. The quantization. step or resolution of an ADC is defined as: (2.3.1). where R represents. the [ull-scale runge (FSR) of the converter and N is.

CHAPTER 2. DIGITAL CONTROL SYSTEMS. 16. the number of converter bits. (Bester, 1999; Van Heerden, 2003; Pease, 2008; Luo. et al., 2005) A quantization. els the converter. error (eq) can occur due to the limited quantization has available. to select from, meaning. truncated. or rounded.. The quantization. quantized. value and the actual sampled value. (Luo. lev-. the signal is either. error is the difference between the. et ol., 2005). eq = quantized value - actual value. (2.3.2). The error will always be in the range 6.. -2 (Bester,. 6.. 2. < eq <. 1999; Van Heerden, 2003).. (2.3.3). From equation. with every added bit, the quantization. (2.3.3) it is evident that. error will be halved.. When selecting an ADC, ac domain specifications. + distortion). lution (ER), signal-to-Inoise bits (ENOB). in varying results.. will provide a measure of how accurately. to the output code. Noise can however result. (Pease, 2008). (signal-to-quantization-noise. La noise power of a signal. determined. the ADC conversion. such as offset error, gain error, differential. and integral nonlinearity. the illput signal will be matched SQNR. or SINAD and effective number of. will provide a measure of how repeatable. will be. Dc domain specifications nonlinearity. such as effective reso-. ratio). The quality. is a ratio of the signal power. of the output. of the ADC can be. by this value. The SQNR of a converter in decibel is ideally defined. as:. 6.02·. TI. +. 1.76 riB. (2.3.4). when' nis equal to the number of bits ill l.hc converter. result of the quantization. noise within the converter.. The SQNR must be large La prevent. unwanted. various types of ADCs and their characteristics. 2.3.2 1\. This noise is as a. (Pease, 2008) quantization. are presented. noise.. The. ill Table 2.1.. The Digital Signal Processor. nsp is necessary. to process and execute control algorithms. mcnts Lo the control algorithm. as determined. and make adjust-. by the feedback or feed-forward..

CHAPTER. 2. DIGITAL. 17. CONTROL SYSTEMS. Table 2.1: 'Types of ADCs (Luo et al., 2005). ADC type. Characteristics. Convert 1 LSB at a time, starting from MSB 1 Bit per clock. Serial. Resolution. Sample rate. Best. Slowest. Flash. Medium. Medium. Two-step, multistep, pipeline. Lowest. Fastest. Examples Single slope, dual slope, successive approximation (SAR), delta-sigma. (.6.B) Flash. Subranging. Conversion period of one clock cycle Combination of serial and parallel techniques. DSPs are well suited as high-performance [or real-time. digital processing. Their architecture. controllers.. and can handle. They have been designed. complex control algorithms.. bas specifically been optimised for digital signal processing. tasks allowing them to perform multiple instructions. per clock-cycle.. However,. they do not generally contain ADCs that are necessary for closed-loop control (du Toit et al., 1995).. of power converters. The way DSPs perform fixed-point. curacy.. Floating-point. arithmetic. Can be classified as either floating- or. offers a wider dynamic. Tt is much simpler to implement. arithmetic. than it is La perform. fixed-point. requires. the scaling of variables.. Floating-point. due Lo their increased complexity. control algorithms. in fixed-point;. careful monitoring. processors. this is due to the fact that errors by. tend to he more expensive. although development (Karipidis,. to lise a floating-point. ac-. in floating-point. of overflow and underflow. saved thanks to their ease of programming. The decision whether. range and increased. costs cau probably be 2001). or fixed-point. DSP was for-. merly based ou cost and ease of usc. This however is HoLas significant anymore. What defines the decision is rather based on the data set required. set requires greater mathematical mat is required.. Floating-point. flexibility and accuracy a floating-point DSPs ofIer real arithmetic,. and a wider dynamic range than fixed-point. The fixed- and floating-point. If the data. (Frantz. for-. higher precision. f!j Simar, 2004). terms refer to the way in which the devices.

CHAPTER. 2. DIGITAL. represent. their numeric data.. metic,. while floating-point. (Frantz. f3 Simar, 2004.). 2.3.3. A fixed-point. DSPs support. The Digital-to-Analog. The structure. 18. CONTROL SYSTEMS. of a digital-to-analog. DSP will perform integer aritheither integer. or real arithmetic.. Converter. converter. (DAC) is simple in compari-. son with an ADC. It can be divided into two components 2.3.3.. The digital signal gets converted. corresponding. as seen in Figure. into an analog signal of magnitude. Lo the digital code. The decoder is used to convert the digital. word into a number of an amplitude-modulated voltage for the duration. of the sarupliug period.. I. Digital input ----. II>I Decoder .... I. I---. I. ...... .___. Figure 2.4: Block diagram of a digital-to-analog. The number of bits determines. pulse. The SIR maintains. the. (Luo et al., 2005). converter.. Analog output. .... S_/H_---'I------.. (Luo et al., 2005). the accuracy of the DAC. DACs are consid-. ered simpler than ADCs since they need only decode the digital input signal, there is little degradation. to the output signal accuracy.. that may occur is if the processor's. The only degradation. data word is greater than that of the DAC. in which case the signal would have to be compensated correct width.. in order to be the. (Van Heerden, 2003). DAC~ can be classified into serial and parallel N. typically requires N or 2. -. devices.. 1 clock cycles to output. A serial device. for an N bit converter.. A parallel device typically requires one clock cycle. (Luo el ol., 2005). 2.4. Research in the Area of Digital Controllers. Tables 2.2 and 2.3 list. a comparison. of controllers. truions [or the control of power electronic used Lo determine (CIRPEC),. the specifications. developed. converters.. at various in Li-. These controllers. for the CIR power electronics. which was designed hy t.hc author.. were. controller.

CHAPTER. 2. DIGITAL. CONTROL SYSTEMS. 19. Table 2.2: Comparison of current digital controllers. Table adapted from Van Heer-. den (2003). Comparison Name Manufacturer DSP Precision Fixed/Floating point MFLOPS MIPS Data bus width Serial ports ADC channels PWM channels PLDs FPGAs EPLDs Memory DSP (internal) RAM ROM /FLASH /EEPROM DSP (External) RAM (SRAM/SDRAM) FLASH/EEPROM Communication RS- 232/SPI/I2 Emulator. C /USB. (DSP /FPGA). Fibre optics Analog inputs Analog outpuls PvVM outpuls Power supply Expansion header. of current. digital. controllers. PEC33 University of Stellenbosch (PEG) TMS320VC33-150 32-bit Floating 150 75 32-bit 1xSPI. UC Virginia Polytechnic (CPES) ADSP-21160M 32-bit Floating 600. 2xEPIK50 2xEPM7256B. 1xXCV 400-4BG560C. 32 kB SRAM. 4 Mb. 512 k (8-bit). EEPROM. RS-232/USB JTAG Ext. 18xTx, 18xRx. Local 2xTx, 2xRx 32 (lO-biL) 8 (12-biL) 2x2xIJ. + 2 (18) 5 V, 2 A (wax) Yes. 64-bit 2xSPI,. 6xlink port. (Unknown). PCI via mezzanine card JTAG IJ.(2xTx, ext. Ou-board ext. 5V Yes. 2xRx). unknown.

CHAPTER. 2. DIGITAL. 20. CONTROL SYSTEMS. Table 2.3: Comparison of current digital controllers continued. Comparison. of current digital controllers. Name. MU -DSP240- LPI. Manufacturer. Monash (PEG). DSP. TMS320F240. Precision Fixed/Floating point MFLOPS MIPS Data bus width. l6-bit Fixed. Serial ports. 20 l6-bit lxSPI, 1 x RS422 /RS485 / RS232. ADC channels PWM channels PLDs FPGAs EPLDs Memory DSP (internal) RAM ROM/FLASH/EEPROM DSP (External) RAM (SRAM/SDRAM). 16 (lO-bit) 12. FLASH /EI'~PROM. 64 le (lG-bit). continued ISEADSP RWTI-I Aachen (ISEA) ADSP-2l060/l/2 (max 2) 32-bit Floating 80 (120 peak) 40 48-bit 2xRS232, RS485/RS422, VMEbus,4xlink port, lxTDM serial port. 6xOrca. 2CA. 544 (16-bit) 16 kB (lG-bit). 2 Mb - 4 Mb. 128 k (16-bit). 32 k - 256 k (48-bit) 512 k - 4 MB (Flash) 16 kB (EEPROM). Communication RS-232/SPT/T2C/USB. RS232. EU1l11ator (DSP /FPGA) Fibre-optics Analog inpu ts Analog outputs PWM outputs Power supply Expansion header. JTAG 10 (10-1)it) 2x4 ±15 V, +5 V. No. 2xRS232, RS485/RS422, VMEb11s JTAG 64 (12/l4-bit) I/O 64 (16-bit) I/O 32 single Yes.

CHAPTER. 2. DIGITAL. CONTROL SYSTEMS. 21. The comparison includes the PEC33 controller developed by Van Heerden (2003) at Stellenbosch University. It succeeded the PEC31 controller presented in Bester et al. (1998); Bester (1999). The PEC33 has a more powerful DSP and faster ADC converters in comparison implements. to its predecessor.. The PEC33. a modular design through expansion headers with all of its 18. PWM outpuls being sent via a fibre optic expansion board. Modular designs have advantages. including the ability to have separate. boards for separate functions that can be removed or added from or to a system whenever necessary. It also serves the purpose of ease of future expansion and upgrading; when a section of the hardware becomes obsolete or outdated only the expansion boards are affected thereby not having to redevelop the entire PCB's contents. However, there are issues inherent to a modular design. By severing the connection. belween boards, via cable or a header, signal integrity is com-. promised and unwanted noise is introduced. into the system.. Track lengths. between devices on a single PCB tend to be shorter and there is the added advantage of a potential solid ground and power plane to further reduce noise. The author of this thesis has attempted. to place as much as is necessary on. the controller PCI3 while at the same time providing modular functionality through the use of expansion headers. The PEC33 controller makes use of two transmit devices. OIl. board as corurnunicatiou. and receive fibre optic. devices, most likely for the distributed. control of power electronics as presented in du Toit et al. (1998). The next controller is the Universal Controller (UC) presented in Francis f!j Boroyevich (2001), Francis (2004) and Francis. et al. (2005) developed at. the Centre for Power Electronics Systems (CPES) at the Virginia Polytechnic Institute. and State University. This particular. controller succeeded the previ-. ous UC developed by Celanovic (2000); Celanovic et al. (2000) which was built around an Analog Devices 21062 SHARC DSP EZ-LAB development system. Improvements. included a more powerful DSP in the form of an ADSP-21160.. The ADSP-21160 has the ability lo be connected in parallel with six more of the same DSPs, allowing for parallel processing.. However, the controller. only consists of one DSP and one FPGA. The ADSP-21160 also comes with a large amount of on-board slatic random access memory (SRAM) (4 Mb). As a result of the UC::; architecture. being specifically designed as an application.

CHAPTER manager. 2. DIGITAL. (main controller). have any on-board. in a distributed. control environment. ADCs and features two transmit. The next controller Power Electronics. single-board. to the DSP is the addition. read only nieuiory (EEPROM). expansion.. of Australia. (Holmes, 2000).. the TMS320F240.. of an electrically. The only device. erasable programmable. The MU-DSP240-LPI. inverters.. developed by the. design based around the digital motor/mo-. tion control DSP from Texas Instruments,. control three-phase. it does not. and receive fibre optics.. in the table is the MU-DSP240-LPI. Group at Monash University. It is a free-standing external. 22. CONTROL SYSTEMS. board was designed to. However, it does not make provision. for I/O. This hoard is an example of a design relying purely on a dedicated. motion control DSP. The final controller in the table is the ISEADSP pidis (2001).. The ISEADSP. research projects. forms the basic control hardware. at the Institute. for Power Electronics. (ISEA) at the Aachen University satile digital architecture/structure and real-time simulation tems.. hardware. of Technology.. for various. and Electrical. Karipidis. for the rapid prototyping. proposed. Drives a ver-. of control units. of loads for power electronic and electrical drive sys-. A single board was proposed. modular. board developed by Kari-. as the basis for a powerful and flexible,. It features. structure.. the FPGAs. design.. All I/O. interfaces. are implemented. ISEADSP. hoards can he stacked up to five hoards deep allowing for a total. of ten processors,. through. a DSP and FPGA. of which there are six. The. 320 analog and 320 digital inputs or outputs.. rack can include 20 ISEADSP. boards.. In this structure. A VMEbus. a single ISEADSP. hoard can feature up to two DSPs. The DSPs selected were from the Analog Devices range' of SHARC ADSP-2106 x devices. 120 milliou floating operations sustained. These DSPs are capable of. per second (MFLOPS). peak and 80 MFLOPS. operation.. Karrpidis performance. established. nsp. that. it was advantageous. La complement. with a device such as all FPGA as this would offer greater. flexibility for I/O related tasks due to the reconfigurable devices.. Karipidis. also established. capable of a sustained. performance. control and simulation. algorithms.. any fibre optic connectors A modular. a high-. application. 011. nature of the FPGA. that the DSP would at least need La be of 40-80 MFLOPS The ISEADSP. the controller. in order to implement. does not make provision for. board itself.. of a digital controller was investigated. at the North.

CHAPTER. DIGITAL CONTROL SYSTEMS. 2.. 23. Table 2.4: Features of the EVMs used by Liu (2005).. Carolina. EVM (central controller). TMS320C6701. Manufacturer Fixed/Floating point DSP Precision Clock MFLOPS MIPS SRAM External data bus Interface. Texas Instruments Floating 32-bit 120/150/167 MHz 1000. EVM (daughterboard). AED-106. Manufacturer FPGA Analog inputs Sample rate. Sigrialware Xilinx XCV300 4x 16-channel (12-bit) 6 MSPS. State. University. 1 Mb 32-bit JTAG. for distributed. (2005); Liu et al. (2005).. power electronic. A new architecture. for modular. systems. by Liu. distributed. con-. trol was proposed by Liu (2005). It is referred to as a hybrid multi tap-inverse star structure. in the literature.. local controllers. The central controller. at each phase-leg using a fibre optic multitap. Using an asynchronous. serial communication. receives the same information information controller. accordingly. straight. A development of a TMS320C670J. interface. signals to the bus interface.. each local controller. from the central controller. Return. and interprets. signals are sent from each individual. the local. back to the central controller via a fibre optic interface. board,. the TMS320C6701. signed by Texas Instruments. hyan. transmits. WR.'i. floating-point. FPGA daughtcrboard,. used. R.<;. evaluation. module. the central controller.. (EVM), deIt consists. DSP. This board was then complemented. the AED-l06 developed by SIGNALWARE.. The. FPGA present on this board is the XCV300 from Xilinx. Some of the features of the two boards arc listed in Table 2.4. Another instance where all EVM was used as the digital controller is by the Colorado Power Electronics Prodie. el. Center at the University. al. (2001) investigated. a digital controller. tching power supply. The ADMC401 evaluation Devices. (2000) was used as the controller. of Colorado at Boulder. for a high-frequency. swi-. module developed by Analog. for a test bed to validate. a de-.

CHAPTER. 2. DIGITAL. sign targeted. CONTROL SYSTEMS. at a low cost standalone. (ASIC). Some of the features the ADMC101 (MIPS). lG-bit fixed-point. ADMC401. features. IL is a 26 million instructions. DSP intended. for motor control applications.. EVM. ADMC401. Manufacturer DSP MIPS Fixed/Floating Precision Analog inputs. Analog Devices ADSP-2171 26 Fixed 16-bit 8-channel (12-bit). paper published. by Mohan. chip. et al., 2001).. & Ang (1994.), a TMS320C30. DSP EVM by Texas Instruments. was used to control a éuk. This DSP is capable of 33.3 MFLOPS. performed. the necessary signal processing algorithms. TLe DSP was interfaced. (AIC) which contains Ang (1991) concluded. 2.5. DPWM. The. PWM units on the ADMC401 could only offer 2-bit. converter.. performance. per second. 2.5: Features of the EVl\J used hy Pronie et. al. (2001).. In a Journal f-loating-point. circuit. in Table 2.5. The DSP core of. at the desired switching frequency of 1 MHz (Prodie Table. signals.. integrated. an eight channel 12-bit ADC. An external. was used as the built-in resolution. application-specific. are presented. is the ADSP-2171.. 24. to a TLC32044. 14-bit resolution. and 16.7 MIPS. The DSP and generated. the PWM. analog interface. controller. ADC and DAC converters.. that a DSP could be used as a controller. Mohan. fj. for a high-. switching converter.. Advantages and Disadvantages of Digital Control Systems. Digital control systems. have many advantages. some of which arc presented 1999; Wilkinson,. over analog control systems,. in Table 2.6. (Martin. 1997; Pctcrchcv. fj Ang, 1995; Duan fj Jin,. & Sanders, 2001; Karipidis, 2001; Pctcrchcv. f1 Sanders, 2003; Prodie et al., 2003; Miao et ol., 2004; Syed et al., 2004; Luo et al., 2005; Milanovic. el al., 2005, 2007).

CHAPTER. 2.. 25. DIGITAL CONTROL SYSTEMS. Table. 2.6: Advantages of digital control systems.. Advantages • There are many design tools that can help shorten the design procedure. • Analog control system circuitries are affected by manufacturer tolerances and external factors such as temperature; whereas software based digital control systems remain largely unaffected by these problems. • Digital systems arc smaller and consume less power when compared to their analog counterparts. • Highly reproducible/repeatable. • Highly reprogrammable. • Highly flexible/versatile; modification of control algorithms can be done without the need to alter hardware. • Less susceptible to aging and environmental variations. • Digital control systems are less susceptible to noise. • Results in a reduction ill the number of external components required. • Results in improved dynamic response. Sorne of the disadvantages 1997; Martin. fj. are presented. in Table 2.7: (du Toit et al., 1995,. Ang, 1995; Bester et al., 1998; Duan. fj. Jin, 1999; Karipidis,. 2001) Table. 2.7: Disadvantages of digital control systems.. Disadvantages • Real-time operation is not inherent to digital control systems and requires careful engineering La balance software and hardware implementations. • Delays occur when converting from the analog to the digital domain. • Signal resolution is determined by a finite word length of a digital controllor..

CHAPTER. 2.6. 2. DIGITAL. CONTROL SYSTEMS. 26. Conclusion. In this chapter the basic control block for a switching converter was presented. This allowed for the basic components required for digital control to be determined, namely an ADC, DAC and DSP. A brief investigation was done on these components. to establish what characteristics. need to be present when. selecting these components for the design. A thorough investigation was done on existing digital controllers to determine which components and what characteristics the components selected had and also for which end applications they had been designed for. This allowed for a generic structure for a digital controller to be conceived. From the investigation a list of advantages and disadvantages are presented and it could be seen that the advantages introduced by digital control outweigh the disadvantages..

Chapter 3 Controller Design and Considerations 3.1. Introduction. This chapter Controller mention. focuses on design and development. specifications. as determined. of the Cm.PEC. hardware.. by the previous chapter are listed and. is given to all the components. of importance.. The controller. tecture overview is provided to give the reader a visual understanding all the components age and current. are linked. The power supply requirements. are presented.. and layout and the challenges. This chapter. archiof how. including volt-. concludes with the PCB design. that need to be considered. at high-switching. frequencies.. 3.2. Controller Specifications. In order Lo make the controller possible, component. the specifications selections. as generic, reprogra.mmable. presented. and flexible as. in Table 3.1 were decided upon.. that satisfy these specifications. detail in this chapter.. 27. are explained. The. in more.

CHAPTER. CONTROLLER. 3.. DESIGN AND CONSIDERATIONS. 28. Table 3.1: Controller specifications.. Controller Programmable processor. signal. Programmable. logic device. Analog-to-digital conversion Sample rate (resolulion) Analog input channels Digital-to-analog conversion Update rate (resolution) Analog output channels Pulse-width modulation outputs inputs. Connectors. Memory User. storage. interfaces. Audio. 3.3. specifications Floating-point processor to compute control algorithms. To perform co-processing and to add design flexibility.. > 100 kSPS (lO-bit). >. 8.. > 100 kHz (12-bit). 2. 10, five complementary. 10 for error signalling. 20xFibre optic (lOxRxjTx) 1x expansion header 1x Universal Serial Bus 2xJTAG. Non-volatile, volatile memory for program and data storage. Push button. Route audio pius from signal processor to PLO.. Controller Overview. A simplified block diagram of the CIRPEC features. pairs.. Cl.. hybr id design consisting of. Cl.. is illustrated. in Figure 3.3.. It. DSP and FPGA. One of the reasons. for this design was due Lo the fad that this controller would be used as a tool for students. and engineers.. largely programmed. This allows for either the FPGA or OSP to be. as separate pieces of hardware.. A large high-speed data and address bus has been implemented to service the major components. synchronous. in order. These include the OSP, FPGA, Flash and. dynamic ralldom access memory (SDRAM). The data bus op-. erates at ] 00 MIb:. The DSP has direct access to the FPGA, SORAM and EEPR.OM. In order for the DSP La access the upper address regions of the FI1-1.o.;h memory, it needs to elo so through the FPGA since there are not enough address pins. Oll. the DSP. This is useful since it allows the FPGA to have read.

CHAPTER. 3. CONTROLLER. DESIGN AND CONSIDERATIONS. 29. and write access to the Flash memory. The DSP generally. performs. computationally. intensive. algorithms. and. therelore needs direct access La external memory such as SDRAM. The FPGA instead is used as a co-processor ality for many components.. to the DSP and performs glue-logic function-. For instance the DSP would need to communicate. via the FPGA La have access to the ADCs. In this case registers may need to be configured in the FPGA to allow communication n. I"l. n. ti',~. JJ DSP TMS320C6720. ==. A A. f=). ~lED[o31@-. 0tIIBll. to7J 11. 1. o. I Rl I. 1. pus~noN. ~. -11. to occur.. FPGA EP1 C12Q240C8N. A 0·1. ~. 11. ADC TLV1570. I. I. EEPROM 24LC1025. ~0. B. ::l I!I. ~. ~' B. 1. ii!. L~. z. 2. n C/). m ",'". SDRAM K4S281632K-U175. I:. §. r---. U. DAC TLV5638. J. "'-. -qlt). I I. L-. J. u:;. 3. FLASH S29AL016D. 1.. 10. ,,'-. FIBRE OPTICS .."..._.,...... 'V. U~. Figure 3.1: Block diagram of the CIRPEC.. 3.4. Controller Components. This section provides more detail into the components in order Lo satisfy presenled. Lhc specifications.. and explanation. the design of the controller.. Features. selected for the CIRPEC. of some of the devices are. is given as La how and where these devices fit into.

CHAPTER. 3.4.1. 3.. CONTROLLER. DESIGN AND CONSIDERATIONS. 30. DSP. A DSP is ideal for high-performance raw computational algorithms.. throughput. controllers.. They have been designed for. and are ideal for processing. real-time. control. One of the things Lo consider when selecting a DSP is whether to. select floating- or fixed-point.. This was mentioned. in Chapter. 2. A floating-. point DSP was thus selected for its greater dynamic range, mathematical ibility, high accuracy. and relative ease of programming.. flex-. The DSP which was. selected is the TMS320C6720. from Texas Instruments.. DSP is provided in Appendix. C.l. This device will be referred to as the C6720. in the text. The TMS320C67x. floating-point. A block diagram of the. DSP's architecture. operates. by. dividing a 32-bit data path into two parts in the form of scientific notation. The one part is a 24-bit mantissa. which can either be used for integer values. or as the base of a real number. and the second part is an 8-bit exponent.. The 24-bits allow for a precision range in the order of lG M and coupled with the 8-bit exponent a fixcd-point. allows for a greater dynamic. format.. The C6720 DSP natively. 32-hit single-precision floating-point dynamic. (SP) floating-point,. arithmetic. bit mantissa. (Fr·auLz. fj. Table 3.2 presents performance. 2008b).. 64-Bit DP utilises a 53-. DP achieves much greater precision and. some of the DSP's. 32-bit floating-point unit (CPU).. CPU is capable of. Cl.. maximum. The CPU is capable floating-point,. of 1200 MFLOPS. (Texas Instruments,. cache.. ('plus') 2006b).. six of which are random. Both are necessary. access when. intensive algorithms. memories. and asyuclirouous. has been configured. C67x+. at 200 MHz at which the. ill parallel each cycle. IL has 64 kB of internal. La external. cycles per. The C6720 is a high-. up to eight instructions,. The CG720 has a 16-biL External. communicate.. features.. The DSP operates. of executing. calculation. to connect. multiple. DSP featuring the enhanced. (RAM) and 32 kB of instruction. performing. (DP). Siuiar, 2004). central processing. SDRAM),. 32-bit fixed-point.. and G4-bit double-precision. (Texas Instruments,. and an l1-bit exponent.. supports. range at the expense of speed as this requires. operation.. memory. range than is possible with. such. Memory 3.<;. Interface. (EMIF). allowing il,. Single Data Rate SDRAM. (SDR. RAM or read ouly memory (ROM). The FPGA. as an asynchronous. memory so that the two devices can. The data movement accelerator. can be used to transfer data between internal. controller. (dMAX) on the DSP. data memory and ally address-.

CHAPTER. 3.. CONTROLLER. DESIGN AND CONSIDERATIONS. 31. Table 3.2: DSP features.. TMS320C6720 CPU Core Precision Clock MFLOPS MMACS Archi teet ure Memory RAM On-Chip Ll/SRAM EM IF GPIO External memory support. C67x+ 32-bit Floating-point 200 MHz 1200 400. VLIW 64 kB 32 kB 16-bit 64 Asyne RAM/ROM,. I C. 2 2 2 Yes lxRTI 1.2 V 3.3 V 144-TQFP. SPI McASP dMax Timers Core voltage 10 voltage Package able memory space including dimensional. external. (ID), two-dimensional. nsp. memory.. (3D) transfers.. from a non-volatile. The controller. that it, eau boo!' from either a serial EEPROM. include one-. If power is removed [rom the. memory.. needs to 10aO the program. device before it can operate normally.. method. These transfers. (2D) and three-dimensional. The DSP has a volatile program hoard then the. SDR SDRAM. has Leeu designed such. or from Flash memory.. to boo!' the DSP is using the USB emulator. memory. Another. which connects via th. join!' test action group (JTAG) pius. 3.4.1.1. Booting. 'I MS320. 672 x devices contain. an on-chip ROM, identified. which contains a core set of Texas Instruments development.. The contents. The CG720 supports. (TI) software for rapid software. of the ROM are presented. one hardware. as 'C9230CIOO',. in Table 3.3.. boo!' mode option.. When the device is.

CHAPTER. 3.. CONTROLLER. DESIGN AND CONSIDERATIONS. 32. Table 3.3: Components of the C9230CIOO ROM. Texas Instruments (2006a) Component. Description. Address. Bootloader (BOOT ROM). On-chip bootloader. OxOOOO0000. DSP /BIOS real-time operating system Optimised math library containing common math functions e.g. cosine, sine, etc. Optimised set of common DSP functions e.g. FIRs, FFTs, vector MAX, etc.. DSP/BIOS. FastRTS. DSPLTB. Ox00030000. Ox0002 COOO. Ox00020000. reset, a program counter is set to start reading at the beginning of the ROM, address space 0 x 0000 0000, where execution. of the bootloader. begins.. The. boot modes which are supported by the bootleader are included in Table 3.4. To summarise,. the CG720 can either be booted from a parallel FLASH device. or from au EEPROM. 2. or inter-integrated CIn.PEC. device using either the serial peripheral. circuit (I C) protocol,. provides both an EEPROM,. device as standaloue. bootable. options.. interface. (SPI). in either slave or master mode. The in I2C mode, and a parallel Thus far only the EEPROM. FLASH has been. used to boot the controller. Table 3.4: Boot options supported by the on-chip bootleader for the C6720. Boot mode. Description. Parallel Flash. Support. [or 8-/16-bit flash -l-wirc SPI, standard protocol. Ifi-bits of address/B bits of data DSP scuds/receives l6-bit data Standard 12C bus protocol. lfi-bits of addrcss/S bits of data Addressing done through the 12C protocol. The DSP sends/receives 8-I)it data. SPlO Master SPIO Slave I2Cl rviaster I2Cl Slave. The bootleader. uses the registers CFGPTNO and CFGPINI. to capture. the. state of various pins at reset. For the C6720 these pins include the SPIO_SOMI (slave out master in), SPIO SIMO (slave in master To select which device to boo. I,. out) and SPIO_CLK pins.. from on the ClR.PEC three external boot mode.

CHAPTER jumpers. CONTROLLER. 3.. are provided. DESIGN AND CONSIDERATIONS. relating. to the three pins.. displayed. in Table 3.5, determine. CIRPEC.. More information. The jumper. 33 positions,. as. in what mode the device will boot on the. on using the bootleader. can be found in Baldwin. (2009). Table 3.5: Boot mode selection [or jumper pins.. Bootmode. Selection. Boot Mode Parallel Flash SPI Master SPI Slave I2C1 Master J2C1 Slave. 3.4.1.2. JPl. JP2. JP3. 2-3 2-3 2-3 1-2 1-2. 1-2 2-3 1-2 2-3 1-2. 2-3 1-2 1-2 1-2 1-2. The Emulator. Another method to boot the DSP is to use a JTAG emulator. PLUS emulator used was developed by Spectrum communication. between a computer. these pieces of hardware.. The XDS510USB. Digital. The emulator allows. and the DSP and is connected in-between. A Tl emulator. is also used for source code debugging.. is necessary to program It allows stepping. the DSP and. through the code on. a line by line basis and the ability lo monitor the values of variables and registers through the Code Composer Studio Integrated. Development. Environment. (CCS IDE) software from Texas Instrumcuts. The JTAG interface has been standardised. as IEEE 1149.1 (Spectrum. ital Inc., 2008). The side that gets connected serial bus (USB) connector.. to the computer. DSP on the CIRPEC. A description. pins is given in Table 3.G. The JTAG interface [or the is presented. in Figure 3.1.1.2 and has been designed Lo. conform with the guidelines sel out in Texas Instrurnents 3.4.1.3. is a universal. The other side of the emulator has a I-l-pin (7 x 2). header which needs to be made provision for on the DSP board. of the JTAG emulator. Dig-. (2003).. Audio Signals. The CG720 has two McASPs (Multichannel. Audio Serial Ports),. of which one. port which call provide up Lo 16 stereo channels using the lIS (12S) Ionnat..

CHAPTER. 3.. CONTROLLER. DESIGN AND CONSIDERATIONS. Table 3.6: DSP 14-pill emulator connector pin description. 2007). DSP 14-pin emulator. connector. 34. (Spectrum Digital Inc.,. pin description. Pin #. Signal. Description. 1 2 3 4,8,10, 12. TMS TRSTTDI. JTAG test mode select. JTAG test reset. JTAG test data input.. Emulator State Output Output Output. Target State Input Input Input. Input. Output. Input. Output. Input. Output. Output. Input. I/O I/O. I/O I/O. GND. 5. PD. 6. 7. KEYED TDO. 9. TCICRET. 11. TCT<. 13 14. EMUO EMU1. Presence detect. Indicates the emulator cable is connected and the target is powered up. JTAG test data output. .JTAG test clock return. Test clock input to emulator. JTAG test clock. 12 MHz clock from emulation pod. Emulation pin O. Emulation pin 1.. The McASP can seamlessly illterface with CODECs, DACs, ADCs and other devices. The McASP supports many variants of the lIS format including time division multiplex (TDM) formats with up to 32 time slots. Considering the CIRPEC was designed with future audio applications in mind at the CrR, these multiplexed signals have been routed to the FPGA where they call then b) routed off-board if necessary.. 3.4.2. FPGA. All FPGA adds to the Ilcxibility of the design. 1:1S. many external components. can be interfaced to its large number of I/O pins. The FPGA selected is an EP I C12Q240C8 Cyclone device developed hy Altera. It will be referred to as an EP1C12 in the text. Table 3.7 lists some of the features of the EP1C12 device. The architecture of the FPGA is configured using complementary metal oxide scmicouductor (CMOS) SRAM which requires configuration data to.

CHAPTER. 3. CONTR.OLLER. DESIGN AND CONSIDER.ATIONS. 35. RJl 4.7K. PJ. u.J. f;_-+_-+. 14. EMUO EMU I. 2. TRST TMS. GND GND GND. IDI. TDO TCK TCK_RET. II. 9. 4 6. GND. GND. 10 12. JTAG. DGND. DGNO. Figure 3.2: JTAG header interface to DSP.. Table 3.7: EPIC12 device features.. Cyclone EPIC12. device features. Logic Elements M4K RAM blocks (128x36 bits) Total RAM bits PLLs Maximum user I/O pins Package Core voltage I/O buffer voltage achieve logic, circuitry. aud interconnects.. 12,060 52 239,616. 2 173 240-PQFP 1.5 V 3.3 V. This is necessary. each time the. FPGA powers up. FPGAs. currently. make provision. for some DSP applications. llite impulse response (FIR) fillers, pseudo-raudom hannel. filtering and auto-correlation. plementing. shift-register. number generators,. and cross-correlation. blocks in embedded. such as ti-. functions. rnultiby im-. memory. This helps to save logic. cells that would otherwise be used to implement. flip-flop logic (Altera Corpo-. ration, 2003). The latest Altera's. FPGAs. allow for an embedded. case the NIOS® II processor. soft-core. processor. block, in. can be logically programmed. into the.

CHAPTER device.. CONTROLLER. 3.. The C/C++. as a hardware (Hansmann,. language. processor. it is recommended. As previously. In a DSP /FPGA. the FPGA. Altera. property. can then be used to program. would.. that. 2004).. intellectual. DESIGN AND CONSIDERATIONS. mentioned. the software. the processor. design however,. be used as a co-processor. also provides. (lP) functions. hybrid. 36. to the DSP. tools in the form of. to get the design up and running quickly.. the function of the FPGA on the CIRPEC. is to. to the DSP. It was therefore necessary to route the. function as a co-processor. Ifi-bit data and 12-bit address lines to the FPGA. The FPGA would then have application. specific modules running concurrent. to the DSP.. The other function of the FPGA is to provide glue-logic and interface with other external. devices.. These included providing. additional. address lines for. the Flash memory if the DSP was needing access to the full address range. The FPGA has been configured such that it has full access to the Flash memory. Other pins routed from the DSP include the multiplexed. McASPO/1. signals,. which include the SPIl, and SPIO signals and other control signals for external asynchronous output. (GPIO). memories.. A large majority. of the DSP general purpose. pins have thus been routed to the FPGA. input. where they can be. used to interface to devices such as ADCs and DACs. Other devices which have been interfaced one DAC, a header or general. La allow for expansion,. signaling,. to the FPGA include two ADCs, four LEDs for troubleshooting. ten fibre optic transmitters. device to iuterface with a computer,. and ten receivers,. and a pushbutton. a USB. for a reset or other user. interaction. 3.4.2.1. Configuration. Each time the FPGJ\ system power-up,. Device. loses power the configuration. a configuration. SRAM configuration. data.. device is required. to load the FPGA with. This process is known as configuration.. vice used is an Altera EPCS4SJ8N configuration.. of the FPGA is lost. At. Table 3.8 presents. and acts as a controller. The de-. in an active serial. the memory size of the device. The configu-. ration typically requires less than 120 ms using serial data at a rate of 20 MHz (Altera Corporation,. 2003).. After configuration,. the FPGA. enters. an initialisation. registers are reset and the I/O pins are enabled. 3.<;. a logic device.. The configuration. mode where the. The FPGA will now operate. and initialisation. processes together. are.

CHAPTER. 3.. CONTROLLER. 37. DESIGN AND CONSIDERATIONS. Table 3.8: Serial configuration device features.. Serial configuration Device Memory size (bits) referred to as command. device. EPCS4S18 4,194,304. mode and normal device operation. is referred to as. user mode. Since the Cyclone devices use SRAM configuration reconfigured. in-circuit. elements they can be. by loading the new configuration. When real-time configuration. is occurring,. the device is placed into command. mode by a device pin. After the new configuration initialised. the device will return to user mode.. 3.4.2.2. Emulator. FPGA JTAG. data into the device.. data has been loaded and. 3.3V. PI 4. ......... ----'. 6 ----, 10. r---i-------'. IIEADER 5X2. 34 ...----:3'7"5". 1ir1. 3 3V. vee vee vee. 7. _. ft. u. MSELO MSELI. r-__">---~'" '--. --;-;'*"~--_7'36". '--. __:o.;.:;.;..::. DCLK 2=5. . ,. I OJ( "CONFlG R2 "+-~::----:-::IO~K""':':':". ['"'"'1. ,. CONI'. 33. 1. '1. nCE. ~~, nCEO.. I UK DONI'. DATAO. 14(" 145 -.. 1. 1. "eONl'IG nSTA11JS CONF _DONE. EPICl2Q240C8N. DUND. DGND. Figure. In order. (,0. 3.3: Connections for the EPCS4 configuration device.. program. the serial configuration. device, EPCS4,. a JTAG. 1Il-.

CHAPTER. 3.. CONTROLLER. terface (IEEE. 1149.1) is required.. header and configuration grammer. DESIGN AND CONSIDERATIONS Figure 3.4.2.2 illustrates. device have been connected. 38. how the JTAG. to the FPGA.. The pro-. used was an Altera USB Blaster download cable. During in-system. programming. of the EPCS4 using the USB Blaster download cable, the cable. pulls nCONFIG low which resets the FPGA down resistor on the FPGA's. and overrides the 10 kD pull-. nCE pin. The cable then uses the DATA, nCS,. ASDf, and DCL/( pins to program. the EPCS4.. is complete, the cable releases the EPCS4's. As soon as the progmmming. four iuterface pins and the FPGA's. nCE pin, and pulses nCONFIG to begin the configuration.. 3.4.3. ADC. An ADC is necessary to convert signals from the analog domain to the digital domain so that it can be processed hy a digital processor. the selection. of. 311. taken into account. and quantization. ADC the factors mentioned. When considering. in Section 2.3.1 need to be. To revise, these include factors such as conversion time. error.. The ADC selected was the TLV1570 developed. by Texas Instruments.. was selected since it satisfied the specifications. presented. the chapter.. in Table 3.9.. Some of the features are presented. at the beginning. It of. Table 3.9: ADC features.. TLV1570 features Architecture SAR Max. sample rate 1.25 MSPS Channels -'--------::8--------Hcsolution 10 bits Reference Int. 2.3 V, 3.8 V Ext. Analog input range +5 V SINAD 60 dB SNR 61 dB SPI i1-J t-cl--:·[:--a-('e-------::~-=-e-s-------CS plug-ill Package. The TLVI570 IL has a uiaxinuuu. is. ii. Yes 20-S0IC. successive approximation. register. (SAR) architecture.. Hample rate of 1.25 MSPS with a uiaxiunnu. input clock.