DC Biasing–BJTs - KUET

EE 2109 Electronics-I

Dr. Mostafa Zaman Chowdhury

Chapter 4:

DC Biasing–BJTs

Biasing

Biasing: The DC voltages applied to a transistor in order to turn

it on so that it can amplify the AC signal.

Operating Point

The DC input establishes an operating or quiescent point called the Q-point.

Which point is best?

The Three States of Operation

• Active or Linear Region Operation

Base–Emitter junction is forward biased Base–Collector junction is reverse biased

• Cutoff Region Operation

Base–Emitter junction is reverse biased

• Saturation Region Operation

Base–Emitter junction is forward biased

Base–Collector junction is forward biased

DC Biasing Circuits

 Fixed-bias circuit

 Emitter-stabilized bias circuit

 Collector-emitter loop

 Voltage divider bias circuit

 DC bias with voltage feedback

Fixed Bias

The Base-Emitter Loop

From Kirchhoff’s voltage law:

Solving for base current:

+V

_CC

– I

_B

R

_B

– V

_BE

= 0

B

BE B CC

R V

I V 



Collector-Emitter Loop

Collector current:

From Kirchhoff’s voltage law:

I B

I

C

 

C C CC

CE V I R

V  

Saturation

When the transistor is operating in saturation, current through the transistor is at its maximum possible value.

R C V CC I Csat 

V CE 0

V 

Load Line Analysis

I

_Csat

I

_C

= V

_CC

/ R

_C

V

_CE

= 0 V V

_CEcutoff

V

_CE

= V

_CC

I

_C

= 0 mA

 where the value of R

_B

sets the value of I

_B

 that sets the values of V

_CE

and I

_C

The Q-point is the operating point:

The end points of the load line are:

Circuit Values Affect the Q-Point

more …

Circuit Values Affect the Q-Point

Circuit Values Affect the Q-Point

Emitter-Stabilized Bias Circuit

Adding a resistor (R

_E

) to the emitter circuit

stabilizes the bias circuit.

Base-Emitter Loop

From Kirchhoff’s voltage law:

0 R

1)I (

- R I -

V _{CC B B}   _{B E}  0 R

I - V - R I -

V

_{CC E E BE E E}





E B

BE B CC

1)R (

R

V - I V





 

Since I

_E

= ( + 1)I

_B

:

Solving for I

_B

:

Collector-Emitter Loop

From Kirchhoff’s voltage law:

CC 0 C V

C R CE I

E V E R

I    

Since I

_E

 I

_C

:

) R (R

– I V

V _CE  _{CC C C}  _E

Also:

E BE

B R CC

B

C C CC E

CE C

E E E

V V

R – I V

V

R I - V V

V V

R I V















Improved Biased Stability

Stability refers to a circuit condition in which the currents and voltages will remain fairly constant over a wide range of temperatures and

transistor Beta () values.

Adding R

_E

to the emitter improves the stability of a transistor.

Saturation Level

V

_CEcutoff

: I

_Csat

:

The endpoints can be determined from the load line.

mA 0 I

V V

C

CC CE





RE RC

VCC IC

CE

0 V V

 



Voltage Divider Bias

This is a very stable bias circuit.

The currents and voltages

are nearly independent of

any variations in .

Approximate Analysis

Where I

_B

<< I

₁

and I

₁

 I

₂

:

Where R

_E

> 10R

₂

:

From Kirchhoff’s voltage law:

2 1

CC B 2

R R

V V R

 

E E E

R I  V

BE B

E V V

V  

E E C C CC

CE

V I R I R

V   

) R (R

I V

V I I

E C

C CC CE

C E









Voltage Divider Bias Analysis

Transistor Saturation Level

E C

Cmax CC

Csat R R

I V

I   

Load Line Analysis

Cutoff: Saturation:

mA 0 I

V V

C

CC CE





V 0 V _CE

R E R C

V CC I C



 

Exact Analysis

DC Bias with Voltage Feedback

Another way to

improve the stability of a bias circuit is to add a feedback path from collector to base.

In this bias circuit

the Q-point is only

slightly dependent on

the transistor beta, .

Base-Emitter Loop

) R (R

R

V I V

E C

B

BE B



CC

 

 

From Kirchhoff’s voltage law:

0 R

– I – V

R – I

R – I

V

_CC



_{C C B B BE E E}



Where I

_B

<< I

_C

:

I C I B

I C

I' C   

Knowing I

_C

= I

_B

and I

_E

 I

_C

, the loop equation becomes:

0 R

I V

R I R

– I

V _CC  _{B C}  _{B B}  _BE   _{B E} 

Solving for I

_B

:

Collector-Emitter Loop

Applying Kirchoff’s voltage law:

R

_E

I

_E

+ V

_CE

+ I’

_C

R

_C

– V

_CC

= 0 Since I

_C

 I

_C

and I

_C

= I

_B

:

I

_C

(R

_C

+

_RE

) + V

_CE

– V

_CC

=0 Solving for V

_CE

:

V

_CE

= V

_CC

– I

_C

(R

_C

+ R

_E

)

Base-Emitter Bias Analysis

Transistor Saturation Level

E C

Cmax CC

Csat R R

I V

I   

Load Line Analysis

Cutoff: Saturation:

mA 0 I

V V

C

CC CE





V 0 V

_CE

R E R C

V CC I C



 

Transistor Switching Networks

Transistors with only the DC source applied can be used as electronic

switches.

Switching Circuit Calculations

C Csat CC

R I  V

dc B Csat

I I

 

Csat CEsat sat

I R  V

CEO cutoff CC

I R  V

Saturation current:

To ensure saturation:

Emitter-collector resistance

at saturation and cutoff:

Switching Time

Transistor switching times:

d r

on t t

t  

f s

off t t

t  

t

_r

=rise time

t

_d

=delay time

t

_s

=storage time

t

_f

=forward time

PNP Transistors

The analysis for pnp transistor biasing circuits is the same

as that for npn transistor circuits. The only difference is that

the currents are flowing in the opposite direction.