This thesis is titled "Analytical Modeling and Temperature Dependence of Threshold Voltage in Cylindrical Gate Fully Depleted Short Channel MOSFET". A new physics-based analytical model for short-channel effects in thin-film fully depleted cylindrical MOSFET gate is presented in this thesis. Analytical expressions for natural length, Ii, threshold voltage, Vth, threshold voltage shift, LlVth, subthreshold swing, S, and drain-induced impedance decrease, DIEL, are derived for cylindrical gate MOSFETs and their response to change in parameters such as gate length, silicon film thickness, drain voltage, etc.
Cylindrical gate MOSFETs exhibit better short-channel effect immunity compared to DG-SOI MOSFETs. Finally, a temperature-dependent analytical model for the threshold voltage in the fully depleted thin-film cylindrical gate MOSFET is also developed using a Gaussian doping profile and compared with that of DG-SOI MOSFETs.
LIST OF PRINCIPAL SYMBOLS AND ABBREVIATIONS
V'hl Threshold voltage associated with n+polysilicon gate V'h2 Threshold voltage associated with p+polysilicon gate.
CHAPTER!
INTRODUCTION
Introduction
The FET of greatest commercial importance is the metal-oxide-semiconductor FET (MOSFET, sometimes called MOST). Field-effect transistors combine the inherent advantages of solid-state devices (eg, small size, low power consumption, and mechanical stiffness) with a very high input impedance and quadrature transfer characteristic, which is particularly suitable for use as voltage amplifiers. Among the members of the FET family and other semiconductor devices, the metal-oxide semiconductor FET or MOSFET has gained particular importance and importance in the last two decades.
The dominant factor behind such a feature is that the MaS transistor is well suited for IC technology, due to the advantages of being simpler or easier to fabricate and its size can be reduced with a lower degree of small geometry effects. Over the past few years, the MOSFET has emerged as the most important electronic device for researchers, replacing its bipolar counterpart and other devices in sales volume and applications.
Choice of Technology
Improvements in processing techniques in subsequent years have resulted in a steadily decreasing chip area and a progressively reduced feature size. Similarly, in 1990, Very Large Scale Integration (VLSI) circuits appeared with 107 - 108 transistors in a single chip. Very recently ULSI (Ultra Large Scale Integration) circuits with billions of transistors are available in the market.
Although the speed of current BJTs is faster than MOS devices, this situation is likely to change in the future. But the speed of a MOS device depends on its gate length, and as shown in the following sections, we will find that a very reduced gate length (less than 0.1 11 m) can be achieved for this device.
Review of the Previous Work on MOSFETs
- Performance of Bulk MOSFETs in VLSI and ULSI Levels
- Scaling in MOSFET Structures
However, when the dimensions of a MOS device go into the deep sub-micrometer regime, the characteristics of a conventional MOSFET become similar to those of a resistor, i.e. field in a reverse-biased drain junction can cause impact ionization and carrier multiplication. The effects of hot electrons can be reduced by using a design called lightly doped drain (LDD) [7], which uses two doping levels, with heavy doping in most of the source and drain regions, but lightly doped in the region adjacent to the channel.
Brew's empirical scaling rule [8] has provided a successful guideline for conventional MOSFET design. We conclude by describing a particular device structure that may realize the promise of a well-functioning, deep submicrometer device operating at room temperature.
Direct Scaling in Bulk MOSFETs
- Scaling Theory ofDG-SOI MOSFETs
- Objectives of the Present Research
- Organisation of the Thesis
As in the case of bulk MOSFETs, the threshold voltage of a dual-gate SOl MOSFET depends on the gate material. The third and fourth terms of the threshold voltage expression (eq. 1.2) depend on the device parameter lox and Is" but their contribution is negligible. But for high-speed and low-power operation in the length regimes deep sub-micrometer gate, I V is also High and negative threshold voltage is also unacceptable.
V'h can therefore be controlled by the interaction between the two gates [18, 19]. The threshold voltage associated with the n+. Because A2 is larger than A!, p+-p+ SOl dual-gate MOSFETs suffer more from the short channel effects than n+-p+ MOSFETs. In the earlier section we showed that the threshold voltage for the long channel device can be given as. where r/l"his the surface potential at VG= V'hand is given by, 1.15).
However, we neglect both charges in the derivation of the short channel model which gives, r/lslh=2r/lF. To improve the accuracy of the model, we will derive the short channel threshold voltage shift using the above approach, but using the original expression for threshold voltage. It is often used for threshold voltage shift due to the drain voltage (DIBL) [21], which is defined by.
The main objective of this research is to develop a novel physics-based analytical model for threshold voltage shift in short-channel MOSFET with fully depleted cylindrical gate. A temperature dependence model of threshold voltage and threshold voltage shift in cylindrical gate MOSFET will also be developed. To develop a novel physics-based analytical model for the threshold voltage shift of a fully depleted thin-film cylindrical gate MOSFET.
To develop a temperature dependence model for the threshold voltage and threshold voltage shift of cylindrical gate MOSFET. To compare the short-channel effects of the new cylindrical gate MOSFET with those of the dual gate SOl MOSFET.
ANALYTICAL MODELLING OF SHORT CHANNEL EFFECTS IN THIN FILM
MOSFET
- Introduction
- Model Development
- Derivation of Cylindrical Natural Length
- Threshold Voltage Shift (~Vth) Model
- Model for Sub-threshold Swing (S-swing)
- Temperature Dependent Model for ~h
In this chapter, analytical models were developed for short-channel effects and the temperature dependence of threshold voltage in MOSFETs with fully depleted cylindrical gates. Where Lc is the gate length and Ie is the so-called natural length, which characterizes the short channel effect. Where ts is; silicon thickness, is tox oxide thickness, Ss; is the permittivity of silicon and Sox is the permittivity of oxide.
The threshold voltage shift for cylindrical gate MOSFET is identical to equation (2.10), replacing aDG with acL from equation (2.10) and is given by. It is often used for threshold voltage shift due to the drain voltage known as DIBL. The same DIBL expression can be used for cylindrical gate MOSFET where aDG is replaced by acL from equation (2.12) and is given by.
The threshold voltage, V,h, is the critical voltage at which the inversion layer forms to a significant extent, causing a rapid increase in inversion charge for higher gate voltages. In other words, the threshold voltage specifies the gate voltage at the onset of strong inversion. In general, a lower threshold voltage is desirable as it allows the use of a small supply voltage and thus lower power consumption.
The nonuniform doping distribution [34] caused by thermal annealing and similar to a Gaussian distribution is given by . 2.19), where Q is the channel implant dose, Rp is the predicted area, and (J" is the standard deviation. Taking into account the boundary conditions as given in [31] and following the approach of [22], the expression for the channel short-threshold voltage is the temperature dependence of the threshold voltage can be obtained by temperature-sensitive parameters such as silicon band gap, built-in potential, Fermi potential, flat band voltage, intrinsic carrier concentration, and ionized doping concentration, whose expressions are given in [34-37].
RESULTS AND DISCUSSIONS
Variation of threshold voltage shift with gate length over the deep-sub-!-lm regime for cylindrical and dual-gate devices. As the gate length increases, the threshold voltage shift decreases and will eventually approach a lower fixed value implying long channel operation (LG> I !-lm) (Fig. 3.2). Variation of threshold voltage shift with drain voltage over the deep-subflow regime for cylindrical and dual-gate devices.
For different values of drain voltage, the variations of threshold voltage shift with alpha, sub-threshold swing (S-swing) with alpha and DIBL with alpha are shown in Fig. Variation of threshold voltage shift with gate length in deep-sub-flm regime for cylindrical and double gate devices. Variation of threshold voltage shift with drain voltage in the deep-sub-flm regime for cylindrical and dual-gate devices.
The variations of threshold voltage with temperature for cylindrical and double gate devices are shown in Fig. The temperature dependence Fermi potential and flatband voltage primarily control this threshold voltage reduction. Since the cylindrical structure has the gate wrapped all the way around the channel, a channel will therefore be formed at a relatively small value of the gate voltage, and the corresponding value of the threshold voltage will be lower than for a double gate device.
An increase in temperature will cause the generation of carriers in the silicon film, which causes the threshold voltage to become negative. Moreover, as the temperature threshold increases, the voltage difference between the long channel (5 !lm) and the short channel (0.2. !lm) decreases. Variation of threshold voltage shift, LlV,h, with gate length, LG, for cylindrical and dual-gate devices.
CONCLUSIONS AND SUGGESTIONS FOR FUTURE RESEARCH
Conclusions
A complete natural length model was developed analytically and its variations with parameters such as silicon film thickness, tsi, and oxide thickness, tox, were investigated. The effects of drain voltage on (i) L1V'h versus alpha, (ii) S-swing versus alpha, and (iii) DIBL versus alpha graphs were also investigated. It is found that the gate in cylindrical device has a greater control over the channel and also a cylindrical device has a higher alpha (a = Ll2A) ratio, thus enabling greater short channel effect immunity and improved sub-threshold characteristics.
The tighter confinement of all directions allows the cylindrical gate MOSFET to be scaled to 29% shorter channel lengths compared to DG-SOI MOSFETs. Finally, a temperature-dependent analysis model for threshold voltage of a cylindrical gate MOSFET was presented using a Gaussian doping distribution profile covering temperature range from 17K to 520K. It is found that although the cylindrical device has higher packing density and reduced short-channel effects than double-gate device, its operation over larger temperature range is limited by the fact that gate loses control of the channel as the temperature increases.
To overcome this problem, the threshold voltage of the cylindrical device can be increased by increasing the concentration of impurities in the channel and/or by gating function control.
Suggestions for Future Research
Dennard, "Design and experimental technology for 0.1,um gate length low-temperature operation FETs," IEEE Electron Dev. Izumi and T Ishii, "0.1 f.1m gate ultrathin film CMOS devices using SIMOX substrate with 80 nrn-thick buried oxide layer," IEDM Tech.
