Ultra-Scaled III-V XOI FETs For Next Generation Logic Application

Nur Kutubul Alam with the title "Ultra-Scaled III-V XOI FETs For Next Generation Logic Application" has been approved by the assessment board for partial fulfillment of the requirements for the degree of (Name of the Degree) in the Department of the Department of Electrical and Electronic Engineering, Khulna University of Engineering & Technology, Khulna, Bangladesh in February 2015. In this research, we address each of the challenges associated with the materialization of XOI FET and propose their solution. They are calculated at the center of the channel at VG = 0.6 V. Inset shows the 1st self-energy of the device.

CBM -Conduction band minima VBM -Valence band minima CNL -Charge neutrality level TOB -Top of the barrier.

Introduction

Scaling issues in MOSFET

Any further scaling of the gate oxide would increase the static leakage of the gate and result in significant power consumption in the off state of the device. At this stage, we abandon the planner technology and adopt a multi-gate structure such as Double-Gate-MOSFET (DGMOS), tri-gate-FinFET, etc. In a multi-gate FET, the channel is electrostatically controlled by gates from several sides of the channel.

Considering all these facts of simple, cheap production and robust manageability, the SOI (or any advanced version) would still be the best option; if the adverse effects of scaling up SOI FETs can be overcome.

Figure 1.1: Power dissipation in CPU for various technologies as a function of the year of introduction (Source: [10]).

Advent of XOI FET

High-k dielectrics can be grown physically thicker than SiO2, which will give the same oxide capacitance. While the process-induced swing of the threshold voltage (Vth) is very common [37], the threshold voltage of such a device can be controlled by applying a back-gate bias. This feature can even be used to dynamically raise or lower Vth circuit by circuit within the chip in response to the need for lower leakage or higher speed.

Therefore, the integration of III-V semiconductors on the Si platform could be the royal road to achieve high-performance miniaturized devices at low power consumption.

Challenges of XOI FET

In addition, III-V semiconductors have a mature and large industry for solid-state lighting and receivers for optical communications [40]. Electron-phonon scattering and the degradation of limited phonon mobility become prominent in very thin channels [47]. This was recently demonstrated in InAs XOI, where the mobility of InAs XOI was strongly dependent on the channel thickness [48].

The study was performed at 200 nm gate length; however, to the best of our knowledge, performance of XOI FET at sub-20 nm regime has not been fully studied.

Objectives of the thesis work

Layout of the thesis work

Device modeling and numerical simulation are very important to optimize the parameters and thus to perform the experiment. Prediction of device behavior before fabrication is the most advantageous feature of device simulation before experimental measurements. Performing a computer simulation is cost-effective compared to making and performing various types of measurements.

Device simulation allows setting different conditions (under which the manufactured device can be damaged) that can be tested inexpensively.

XOI device structure

Energy of electron in conduction

Mathematical Modeling of IV Characteristics

Ballistic transport theory

The amount of carrier flow depends on the number of energy states within the channel located between the two chemical potentials. So, increasing the number of energy levels in the channel leads to increasing the number of traveling electrons. Since the current is defined as the charge transferred per unit time, the total current through the channel depends on the amount of carrier in motion, i.e., the number of energy states in the channel and on the speed with which the electrons move. 49].

That is why the speed of the carrier is expressed by the injection speed, which is determined only by the band structure of the channel.

NEGF Formulation

Quantum Transport Simulation Using Mode Space Approach

For nanoscale transistors, it is more convenient to solve the Schrdinger equation in mode space (MS) [65,66] where the computational burden is affordable. In the NEGF framework, a suitable basis function set is chosen in terms of which operators such as the Hamiltonian operator and the Green's function are represented. Enforce the closed boundary condition if subbands or modes arise from the two interfaces.

The subbands are the eigenfunctions associated with the confinement in the gate confinement direction (y direction in Figure 2.1). The subbands of the structure are obtained by solving a 1D Schrodinger equation in the y-direction with each vertical slice, positioned at x=x/, along the x-direction. Where χ(n)(x/, y) is the eigenfunction in the y direction at x=x/ and E(n)(x/) represents the bottom of the subband at x/ and n is the subband index.

Applying equation 2.10 to each node along the vertical slice x/ and then applying a closed boundary condition at the semiconductor insulator interface yields a set of linear equations and forms it in matrix form:. The same is used in the XOI FET discretization. 2.11) Equation 2.11 is an eigenvalue problem that can be solved for different subbands. As stated in the previous paragraph, only a few subbands are considered and consequently the summation is truncated at n= Nm.

The channel of the ultrathin body XOI FET is completely depleted, and the shape of the potential Ec(x,y) along the y direction varies slowly with the x position, therefore the variation of χ with x can be neglected, and equation 2.13 becomes . Then the transmission coefficient of the mth mode from the source contact to the drain contact is defined in terms of the Greens function and the expansion function as-.

Figure 2.3: A model of any geometric space divided into vertical slices. The horizontal spacing between the slices is ∆x

Mathematical Modeling for Capacitance-voltage (CV) Characteristics

• Channel Thickness dependent Performance
• Impact of Interface Trap States
• Channel material dependent performance (InGaSb vs InAsSb)
• Effect of Different Gate Oxide having Same EOT
• Traditional XOI FET vs Junctionless XOI FET

However, the actual position of the 1st eigengene depends on the potential in the channel, which is obtained from Poisson's equation. At the vertical edge of the device (the interface of the gate and the high-k oxide in Figure 2.1) is the limit of Poisson's equation (VG + Vbi), where Vbi is the built-in potential. We then calculate the thickness-dependent ID-VG characteristics of the InGaSb XOI FET at a drain voltage of 0.05 V, shown in Fig.

When the highest value of the 1st eigen falls below the source Fermi level (0 eV), the conduction of the carrier takes place. The highest value of EC and that of the 1st proper of the device, along its thickness (y direction). As a result, the 1st eigenlevel of the thinnest channel (3 nm) is at the lowest energy with respect to the Fermi level (0 eV).

Due to the non-parabolism in the dispersion, the effective mass in the UTB channel becomes slightly higher than the bulk [77]. In this figure, the comparison of ID-VG characteristics of InGaSb and InAsSb XOI FETs is shown at VD=0.05V. The thickness of the device body is 3 nm. The highest point of electronic potential (band diagram) in the channel is called the barrier peak, which is

Equation (3.1) shows that the drain current is proportional to the square root of the effective mass. The threshold voltage as well as the AF current of the device depends on the barrier height at zero gate bias. To illustrate this scenario, the ID-VG characteristics are plotted at VD=0.05 V of the InGaSb XOI FET using two gate dielectrics shown in FIG.

The nature of the conduction band is also responsible for determining the threshold voltage of two devices.

Figure 3.1: Tight binding dispersion of GaSb ultra-thin-body with (001) confinement and [100] transport direction

Capacitance voltage (CV) Characteristic of XOI FET

• Effect of channel thickness
• Effect of channel composition
• Effect of doping
• Effect of temperature

This trap behavior in the CV characteristics of the XOI FET is quite different from that reported for conventional SOI and bulk MOSFETs [95, 96]. With increasing gate bias (VG), the eigenlevels move downward (since the Fermi level is held fixed at 0 eV). As a result, no steps or CCRs are observed in the CV characteristics at high channel thickness (FIG. 3.19).

The large separation between 1st and 2nd own causes the CCRs to appear in the CV curves. To further elucidate the 1st and 2nd stage CCR (FIG. 3.3), the composition-dependent 1st and 2nd eigenenergies are plotted in FIG. It reveals that the difference between 1st and 2nd eigenenergies for a given surface electric field (or respective gate bias) decreases with increasing Ga composition.

As a result, the gate bias required for the transition from 1st to 2nd stage CCR decreases with increasing Ga composition, causing the CV curves to shift to the left (FIG. 3.21). The CV curves shift to the left (from positive to negative gate bias) with increasing doping concentration. To explain the CV characteristics of FIG. 3.24 is the band diagram together with the 1st and 2nd eigenlevels shown in FIG. 3.25 for different doping concentrations and VG=3 V.

It is observed that the capacitance in each CCR is independent of temperature, T; but the slope of the transition from the minimum point to 1st step CCR and so from 1st to 2nd step becomes steeper with decreasing T. Therefore, the results of the study on long channel XOI FET are not valid in this regime.

Figure 3.19: CV profile of In 0.3 Ga 0.7 Sb XOI FET as a function of channel thickness.

Recommendation of future work

Colinge and Jean-Pierre Colinge “Multigate transistors as the future of classical metal oxide and semiconductor transistors, Nature, Vol.479, p. Hu, “High-field transport of inversion-layer electrons and holes including velocity overshoot,” IEEE Transaction on Electron Devices, vol. 44, no. Lee et al., “Modeling of CMOS Tunneling Currents Through Ultrathin Oxide Due to Conduction and Valence Band of Electron and Hole Tunneling,” IEEE Transaction on Electron Devices, no.

Chan, “Self-aligned, electrically separable dual-gate MOS transistor technology for dynamic threshold voltage application,” IEEE Transactions on Electron Devices , vol. Hu, “FinFET-self-aligned dual-gate MOSFET scalable to 20 nm,” IEEE Transactions on Electron Devices , vol. 44] Cheng-Li Lin, Yu-Ting Chen, Fon-Shan Huang, Wen-Kuan Yeh, and Chien-Ting Lin “Effect of SOI Thickness-Induced Oxide Traps on the Reliability of Fully Silicide Metal Gate Biased SOI MOSFETs IEEE Electron Device Lett., volume 31, no. 2, p. 165-167, February 2010.

45] Hui Fang, Steven Chuang, Kuniharu Takei, Ha Sul Kim, Elena Pils, Ching-Hung Liu, Sanjay Krishna, Yu-Lun, Chueh og Ali Javey “Ultrathin-Body High-Mobility InAsSb-on-Insulator Field-Effect Transistors , IEEE elektronenhed lett., vol.33, nr.4, s. 53] Langreth, D.C, “In Linear and Non- Linear Electron Transport in Solids NATO Advanced Study Institute Series B, Vol.17, s.3 Plenum, New York, 1976. Lundstorm, "NanoMOS 2.5: A Two-dimensional simulator for quantum transport in Double-gate MOSFETs, IEEE Transaction on Electron Devices, Vol.50, pp.

Hueting, "Validity of the parabolic effective mass approximation in silicon and germanium n-MOSFETs with different crystal orientations, IEEE Transaction on Electron Devices, Vol. 94] Cheng-Li Lin, Yu-Ting Chen, Fon-Shan Huang, Wen-Kuan Yeh and Chien-Ting Lin The Impact of Oxide Traps Caused by SOI Thickness on Reliability of Fully Silicide-Metal-Gate-Strained SOI MOSFET IEEE Electron Device Lett., Vol.31, No.2, pp.165-167, February 2010.