Pooriam Lecture 4

(1)

EECS 31L:

Introduction to Digital Design Lab

Lecture 4

The Henry Samueli School of Engineering

Electrical Engineering and Computer Science

University of California, Irvine

(2)

Lecture 4: Quiz

(3)

Lecture 4: Quiz – Q1

What is the decimal value of signal x ?

SIGNAL

x: SFIXED(2 DOWNTO -5);

x <= “10101000";

(4)

To which predefined data type none of the signals below

can

belong to?

a) STRING

b) BOOLEAN

c) INTEGER

d) STD_LOGIC_VECTOR

a <= '1';

b <= "FALSE";

d <= "0000000Z";

e <= 10001;

f <= 50_000_000;

g <= (OTHERS => 'Z');

(5)

How many times the GENERATE statement will iterate?

a) 15

b) 16

c) 7

d) 8

e) 0

SIGNAL

x:

BIT_VECTOR

(7

DOWNTO

0);

SIGNAL

y:

BIT_VECTOR

(15

DOWNTO

0);

SIGNAL

z:

BIT_VECTOR

(7

DOWNTO

0);

...

G1:

FOR

i

IN

y’

LOW TO

Z’

LEFT GENERATE

z(i) <= x(i)

AND

y(i+8);

(6)

How many errors exists in the following code?

a) 0

b) 1

c) 2

d) 3

e) 4

LIBRARY

ieee;

USE

ieee.std_logic_1164.

ALL

;

---ENTITY

encoder2

IS

PORT

( x: INOUT STD_LOGIC_VECTOR (7

DOWNTO

0);

y: BUFFER STD_LOGIC_VECTOR (2

DOWNTO

0));

END

encoder2;

---ARCHITECTURE

encoder2

OF

encoder

IS

BEGIN

WITH

x

SELECT

(7)

EECS 31L - Final Exam

There are some errors in the following code. Find and correct them.

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

---ENTITY encoder2 IS

PORT ( x: INOUT STD_LOGIC_VECTOR (7 DOWNTO 0); y: BUFFER STD_LOGIC_VECTOR (2 DOWNTO 0));

END encoder2;

---ARCHITECTURE encoder2 OF encoder IS BEGIN

WITH x SELECT

y := "000" WHEN "00000001", "001" WHEN "00000010", "010" WHEN "00000100", "011" WHEN "00001000", "100" WHEN "00010000", "101" WHEN "00100000", "110" WHEN "01000000", "111" WHEN "10000000";

(8)

Lecture 4: Outline

• Sequential Coding

• IF, CASE, LOOP

• Storage Elements

(9)

Lecture 4: Combinational vs Sequential logic

• By definition, combinational logic is that in which the output of the

circuit depends solely on the current inputs. It is then clear that, in

principle, the system requires no memory and can be implemented

using conventional logic gates.

• In contrast, sequential

logic is defined as that in which the output does

depend on previous inputs. Therefore, storage elements are required,

which are connected to the combinational logic block through a

(10)

Lecture 4: Sequential Coding

•

Sequential Circuits

(11)

•

Sequential Circuits

(12)

•

PROCESS

Statement



Only PROCESS, FUNCTION, and PROCEDURE are sequential



Last two called subprograms



PROCESS: for main code; Subprograms: mainly for libraries



Only purely sequential statements are IF, WAIT, CASE, LOOP



These statements can only go inside sequential units

(13)

•

PROCESS

Statement

[label:]

PROCESS

[(sensitivity_list)] [

IS

]

[declarative_part]

BEGIN

sequential_statements_part

END PROCESS

[label];

(14)

•

PROCESS

Statement

[label:]

PROCESS

[(sensitivity_list)] [

IS

]

[declarative_part]

BEGIN

sequential_statements_part

END PROCESS

[label];

PROCESS

(clk, rst)

BEGIN

IF

rst='1'

THEN

q <= '0';

ELSIF

clk'

EVENT AND

clk='1'

THEN

q <= d;

END IF

;

Syntax

(15)

•

Sensitivity list

A list of signals a process is sensitive to.



The sensitivity list is a compact way of specifying the set of signals, events

on which may resume a process. A sensitivity list is specified right after the

keyword process (Left example).



Upon initialization, all processes are executed once

(16)

•

Sensitivity list



on which may resume a process. A sensitivity list is specified right after the



Upon initialization, all processes are executed once



After that, processes are executed in a data-driven manner, they are

activated by events on signals in the sensitivity list of the process, or

PROCESS

(clk, rst)

BEGIN

IF

rst='1'

THEN

q <= '0';

ELSIF

clk'

EVENT AND

clk='1'

THEN

q <= d;

(17)

•

Sensitivity list



on which may resume a process. A sensitivity list is specified right after the



Upon initialization, all processes are executed once



After that, processes are executed in a data-driven manner, they are

activated by events on signals in the sensitivity list of the process, or



By waiting for the occurrence of specific events using the wait statement.



The sensitivity list is equivalent to the wait on statement, which is the last

statement of the process statement section (Right example).

PROCESS

(clk, rst)

BEGIN

IF

rst='1'

THEN

q <= '0';

ELSIF

clk'

EVENT AND

clk='1'

THEN

q <= d;

END IF

;

END PROCESS

;

PROCESS

BEGIN

IF

rst='1'

THEN

q <= '0';

ELSIF

clk'

EVENT AND

clk='1'

THEN

q <= d;

END IF

;

WAIT ON

clk, rst;

(18)

Lecture 4: Sequential Coding

•

VARIABLE



Can only be declared inside a piece of sequential code (in a PROCESS, for example)



Its value is always local



Its value can never be passed out of the PROCESS directly; if necessary, then it must be

assigned to a SIGNAL.



The update of a VARIABLE is immediate, that is, we can promptly count on its new value in

the next line of code

(19)

• Purely sequential statements:



IF



WAIT



CASE



LOOP

(20)

•

IF Statement

IF

conditions

THEN

assignments;

ELSIF

conditions

THEN

assignments;

ELSE

assignments;

END IF

;

IF

x=a

AND

y=b

THEN

output <= '0';

ELSIF

x=a

AND

y=c

THEN

output <= '1';

ELSE

output <= 'Z';

END IF

;

(21)

•

IF Statement



One of the most typical errors with the

IF

statements is to skip the space

between

END

and

IF

, at the end of the statement, and writing it as

ENDIF

.



IF

is a sequential statement that cannot be used in the

concurrent

statements

section of an architecture.

IF

Status = RUN THEN

IF

Code_of_Operation = CONC THEN

F := Operand_1 &

Operand_2 ;

ELSE

F := "00000000";

END IF;

Output_1 <= F;

END IF;

More Examples

SIGNAL

opcode : Bit_Vector(1 DOWNTO

0);

I3: IF

opcode(1) = '1' THEN

F := Operand_1 + Operand_2;

ELSIF

opcode(0) = '1' THEN

F := Operand_1 - Operand_2;

ELSE

(22)

Lecture 4: Sequential Coding

• Example: 1-digit Decimal Counter

ENTITY

counter IS

PORT

(clk: IN BIT;

count: OUT

INTEGER RANGE

0 TO 9);

END ENTITY;

ARCHITECTURE

counter OF

counter IS

BEGIN

(23)

• Example: 1-digit Decimal Counter

ENTITY

counter IS

PORT

(clk: IN

BIT;

count: OUT

INTEGER RANGE

0 TO

9);

END ENTITY;

ARCHITECTURE

counter OF

counter IS

BEGIN

PROCESS(clk)

VARIABLE temp: INTEGER RANGE 0 TO 10;

BEGIN

IF (clk'EVENT AND

clk='1') THEN

temp := temp + 1;

IF

(temp=10) THEN

temp := 0;

END IF;

count <= temp;

END PROCESS;

(24)

• Example: Shift Register

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY shift_register IS

GENERIC

(N: INTEGER := 4); --number of stages

PORT (din, clk, rst: IN STD_LOGIC;

dout: OUT STD_LOGIC);

END ENTITY;

(25)

Lecture 4: GENERIC

•

GENERIC

An interface

constant

declared in a component declaration, or an entity declaration.

Generics provide a channel for

static

information to be communicated to a block from its

environment. Unlike constants, however, the value of a generic can be supplied

externally, either in a component instantiation statement or in a configuration specification.

ENTITY

CPU is

GENERIC

(

BusWidth

: Integer := 16);

PORT(databus : inout Std_Logic_Vector(

BusWidth

-1 DOWNTO

0));

(26)

• Example: Shift Register

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY shift_register IS

GENERIC

(N: INTEGER := 4); --number of stages

PORT (din, clk, rst: IN STD_LOGIC;

dout: OUT STD_LOGIC);

END ENTITY;

ARCHITECTURE shift_register OF shift_register IS

BEGIN

PROCESS (clk, rst)

VARIABLE q: STD_LOGIC_VECTOR(0 TO N-1);

BEGIN

IF (rst='1') THEN

q := (OTHERS => '0');

ELSIF (clk'EVENT AND clk='1') THEN

q := din & q(0 TO N-2);

END IF;

(27)

•

Wait Statement

The wait statement is a statement that causes suspension of a process or a procedure. .

Resuming the process or procedure depends on meting the condition(s) specified in the

wait statement. There are three types of conditions supported with wait statements:

WAIT;

WAIT ON

signal_list;

WAIT UNTIL

condition;

(28)

•

CASE Statement

The case statement selects for execution one of several alternative sequences of

statements; the alternative is chosen based on the value of the associated expression.

CASE

identifier

IS

WHEN

value => assignments;

WHEN

...

(29)

•

CASE Statement

The case statement selects for execution one of several alternative sequences of

statements; the alternative is chosen based on the value of the associated expression.

CASE

identifier

IS

WHEN

value => assignments;

WHEN

...

END CASE

;

CASE

sel

IS

WHEN

0 => y <= a;

WHEN

1 => y <= b;

WHEN OTHERS

=> y <= c;

END CASE

;

(30)

•

CASE Statement

Depending on the values of the variable x and y, we assign the values 0, 1, 2 or 3 (in the

second case) to the signals Out_1 and Out_2 (both of type Integer).

P1:PROCESS

VARIABLE

x: Integer

RANGE

1

TO

3;

VARIABLE

y: BIT_VECTOR (0

TO

1);

BEGIN

C1:

CASE

x

IS

WHEN

1 => Out_1 <= 0;

WHEN

2 => Out_1 <= 1;

WHEN

3 => Out_1 <= 2;

END CASE

C1;

C2:

CASE

y

IS

WHEN

"00" => Out_2 <= 0;

WHEN

"01" => Out_2 <= 1;

WHEN

"10" => Out_2 <= 2;

WHEN

"11" => Out_2 <= 3;

END CASE

C2;

(31)

•

CASE Statement

When two or more alternatives lead to the same sequence of operations then they can be

specified as a multiple choice in one when clause.

P2:PROCESS

TYPE

Codes_Of_Operation

IS

(ADD,SUB,MULT,DIV);

VARIABLE

Code_Variable: Codes_Of_Operation;

BEGIN

C3:

CASE

Code_Variable

IS

WHEN

ADD | SUB => Operation := 0;

WHEN

MULT | DIV => Operation := 1;

END CASE

C3;

END PROCESS

;

(32)

Lecture 4: Sequential Coding

•

CASE Statement

Slices can be used as choices. In such a case, the slice name must come from the

discrete range of the expression type.

P3:

PROCESS

TYPE

Some_Characters

IS

('a','b','c','d','e');

VARIABLE

Some_Characters_Variable: Some_Characters;

BEGIN

C4:

CASE

Some_Characters_Variable

IS

WHEN

'a' to 'c' => Operation := 0;

WHEN

'd' to 'e' => Operation := 1;

END CASE

C4;

END PROCESS

;

(33)

•

CASE Statement

Constant used as a choice.

P5:

PROCESS

VARIABLE

Code_of_Operation : INTEGER range 0

TO

2;

CONSTANT

Variable_1 : INTEGER := 0;

BEGIN

C6:

CASE

Code_of_Operation

IS

WHEN

Variable_1 | Variable_1 + 1 => Operation := 0;

WHEN

Variable_1 + 2 => Operation := 1;

END CASE

C6;

END PROCESS

;

(34)

•

CASE Statement

If the Code_of_Address variable is equal to ‘a’ and ‘c’, then the assignment Operation:=0;

will be chosen. For the ‘b’, ‘d’ and ‘e’ values, the assignment Operation:=1; will be

performed.

P6:

PROCESS

TYPE

Some_Characters

IS

('a','b','c','d','e');

VARIABLE

Code_of_Address : Some_Characters;

BEGIN

C7:

CASE

Code_of_Address

IS

WHEN

'a' | 'c' => Operation := 0;

WHEN OTHERS

=> Operation := 1;

END CASE

C7;

END PROCESS

;

(35)

•

LOOP Statement

Statement that includes a sequence of statements that is to be executed repeatedly, zero

or more times.

[label:]

FOR

identifier

IN

range

LOOP

(sequential statements)

END LOOP

[label];

FOR

i

IN

x'

RANGE LOOP

x(i) <= a(M-i)

AND

b(i);

END LOOP

;

(36)

•

LOOP Statement

The process (which is a clocking signal generator) contains a loop without an iteration

scheme, which will iterate indefinitely.

More Example

SIGNAL

Clock : BIT := '0';

...

Clk_1:

PROCESS

(Clock)

BEGIN

L1:

LOOP

Clock <=

NOT

Clock

AFTER

5 ns;

END LOOP

L1;

(37)

•

LOOP Statement

The infinite loop becomes in practice a finite, as the iterations will terminate as soon as

the variable A becomes greater than 10.

More Example

L2:

LOOP

A:= A+1;

EXIT

L2

WHEN

A > 10;

(38)

Lecture 4: Sequential Coding

•

LOOP Statement

The loop L3 will be repeated as long as the value of the variable it is not greater than 8.

When it reaches the value of 9 the loop is no longer repeated.

More Example

Shift_3:

PROCESS

(Input_X)

VARIABLE

i : POSITIVE := 1;

BEGIN

L3:

WHILE

i <= 8

LOOP

Output_X(i) <= Input_X(i+8)

AFTER

5 ns;

i := i + 1;

END LOOP

L3;

(39)

Lecture 4: Sequential Coding

•

LOOP Statement

The loop statement parameter count_value will cause the loop to execute 8 times, with

the value of count_value changing from 1 to 8.

More Example

Shift_4: PROCESS

(Input_X)

BEGIN

L4: FOR

count_value

IN

1 TO

8 LOOP

Output_X(count_value) <= Input_X(count_value + 8) AFTER

5 ns;

END LOOP

L4;

(40)

Lecture 4: Sequential Coding

•

LOOP Statement

The subtype Range_Type defines the range of integer values from 1 to 8. The parameter

count_value changes according to this specification, i.e. from 1 to 8.

More Example

Shift_5: PROCESS

(Input_X)

SUBTYPE

Range_Type

IS

POSITIVE RANGE

1 TO

8;

BEGIN

L5: FOR

count_value

IN

Range_Type

LOOP

Output_X(count_value) <= Input_X(count_value +8) AFTER

5 ns;

END LOOP

L5;

(41)

Example: Ripple Carry Adder

LIBRARY ieee;

USE ieee.std_logic_1164.ALL; ENTITY adder IS

GENERIC (length : INTEGER := 8);

PORT ( a, b: IN STD_LOGIC_VECTOR (length-1 DOWNTO 0); cin: IN STD_LOGIC; s: OUT STD_LOGIC_VECTOR (length-1 DOWNTO 0); cout: OUT STD_LOGIC); END adder;

ARCHITECTURE adder OF adder IS BEGIN

(42)

Lecture 4: Sequential Coding

Example: Ripple Carry Adder

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY adder IS

GENERIC (length : INTEGER := 8);

PORT ( a, b: IN STD_LOGIC_VECTOR (length-1 DOWNTO 0); cin: IN STD_LOGIC; s: OUT STD_LOGIC_VECTOR (length-1 DOWNTO 0); cout: OUT STD_LOGIC);

END adder;

ARCHITECTURE adder OF adder IS BEGIN

PROCESS (a, b, cin)

VARIABLE carry : STD_LOGIC_VECTOR (length DOWNTO 0);

BEGIN

carry(0) := cin;

FOR i IN 0 TO length-1 LOOP

s(i) <= a(i) XOR b(i) XOR carry(i);

carry(i+1) := (a(i) AND b(i)) OR (a(i) AND carry(i)) OR (b(i) AND carry(i)); END LOOP;

cout <= carry(length);

(43)

LIBRARY ieee;

USE ieee.std_logic_1164.ALL; ENTITY full_adder IS

PORT (In1, In2, cin : IN std_logic; sum, cout : OUT std_logic); END full_adder;

ARCHITECTURE behavioral OF full_adder IS

END ARCHITECTURE;

• Example: Communication between Processes (Full Adder)

HA1

HA2

cin In1 In2

(44)

LIBRARY ieee;

ARCHITECTURE behavioral OF full_adder IS SIGNAL s1, s2, s3:std_logic;

BEGIN

HA1

HA2

cin In1

In2

cout sum

s1

(45)

Lecture 4: Sequential Coding

LIBRARY ieee;

BEGIN

HA1: PROCESS(In1, In2) -- process describing the 1st half adder BEGIN

END PROCESS HA1;

HA2: PROCESS(S1, cin) -- process describing the 2nd half adder BEGIN

END PROCESS HA2;

OR1: PROCESS (s2, s3) -- process describing the 2 input OR gate BEGIN

(46)

Lecture 4: Sequential Coding

LIBRARY ieee;

BEGIN

HA1: PROCESS(In1, In2) -- process describing the 1st half adder BEGIN

s1 <= (In1 XOR In2); s2 <= (In1 AND In2); END PROCESS HA1;

HA2: PROCESS(S1, cin) -- process describing the 2nd half adder BEGIN

sum <= (s1 XOR cin); s3 <= (s1 AND cin); END PROCESS HA2;

OR1: PROCESS (s2, s3) -- process describing the 2 input OR gate BEGIN

cout <= (s2 OR s3);

(47)

• Example: Barrel Shifter

LIBRARY

ieee;

USE

ieee.std_logic_1164.ALL;

ENTITY

barrel IS

GENERIC

(n: INTEGER := 8);

PORT

(inp: IN

STD_LOGIC_VECTOR (n-1 DOWNTO

0);

shift: IN

INTEGER RANGE 0 TO

1;

outp: OUT

STD_LOGIC_VECTOR (n-1 DOWNTO

0));

END

barrel;

ARCHITECTURE RTL

OF barrel

IS

BEGIN

(48)

• Example: Barrel Shifter

LIBRARY

ieee;

USE

ieee.std_logic_1164.

ALL

;

ENTITY

barrel

IS

GENERIC

(n: INTEGER := 8);

PORT

(inp:

IN

STD_LOGIC_VECTOR (n-1

DOWNTO

0);

shift:

IN

INTEGER RANGE 0

TO

1;

outp:

OUT

STD_LOGIC_VECTOR (n-1

DOWNTO

0));

END

barrel;

ARCHITECTURE

RTL

OF

barrel

IS

BEGIN

PROCESS (inp, shift)

BEGIN

IF (shift=0) THEN

outp <= inp;

ELSE

outp(0) <= '0';

FOR i

IN 1 TO inp'HIGH LOOP

outp(i) <= inp(i-1);

END LOOP;

(49)

Lecture 4: Storage Elements

•

Latch



Positive-Level D Latch with asynchronous reset



Negative-Level D Latch with asynchronous reset

•

Flip-Flop

•

Positive-Edge D Flip-Flop with synchronous reset

•

Negative-Edge D Flip-Flop with synchronous reset

•

Positive-Edge D Flip-Flop with asynchronous reset

•

Negative-Edge D Flip-Flop with asynchronous reset

(50)

(51)

•

Clock

d

q

rst

d

q

rst

d

q

rst_s

d

q

(52)

•

Clock

d

q

(53)

•

Clock

d

q

(54)

•

Clock

d

q

(55)

•

Clock

d

q

(56)

•

Clock

d

q

(57)

•

Clock

d

q

(58)

•

Clock

d

q

(59)

•

Clock

d

q

(60)

•

Latch



d

q

rst

LIBRARY ieee;

USE ieee.std_logic_1164.ALL; ENTITY PDL IS

PORT (d, en, rst: IN STD_LOGIC; q : OUT STD_LOGIC);

END PDL ;

ARCHITECTURE RTL OF PDL IS BEGIN

PROCESS ( ? , ? ) BEGIN

IF (? = ’?1’) THEN ? <= ’?’;

ELSIF (? = ’?’) THEN ? <= ?;

(61)

Lecture 4: Storage Elements

•

Latch



d

q

rst

LIBRARY ieee;

USE ieee.std_logic_1164.ALL; ENTITY PDL IS

END PDL ;

ARCHITECTURE RTL OF PDL IS BEGIN

PROCESS (rst, en) BEGIN

IF (rst = ’1’) THEN q <= ’0’;

ELSIF (en = ’1’) THEN q <= d;

(62)

•

Latch



Negative-Level D Latch with asynchronous reset

d

q

rst

LIBRARY ieee;

USE ieee.std_logic_1164.ALL; ENTITY NDL IS

END NDL;

ARCHITECTURE RTL OF NDL IS BEGIN

PROCESS (rst, en) BEGIN

IF (rst = ’1’) THEN q <= ’0’;

ELSIF (en = ’0’) THEN q <= d;

END IF; END PROCESS; END RTL;

d

q

(63)

Lecture 4: Storage Elements

•

Flip-Flop



LIBRARY ieee;

USE ieee.std_logic_1164.ALL; ENTITY PDFF IS

PORT (d, clk, rst_s: IN STD_LOGIC; q : OUT STD_LOGIC);

END PDFF;

ARCHITECTURE RTL OF PDFF IS BEGIN

PROCESS (rst_s, clk) BEGIN

IF ( ? ) THEN

IF (rst_s = ’1’) THEN q <= ’0’;

ELSE

q <= d; END IF; END IF; END PROCESS; END PDFF;

d

q

(64)

•

Flip-Flop



LIBRARY ieee;

END PDFF;

ARCHITECTURE RTL OF PDFF IS BEGIN

IF (clk’EVENT AND clk =’1’) THEN IF (rst_s = ’1’) THEN

q <= ’0’; ELSE

q <= d; END IF; END IF; END PROCESS; END PDFF;

d

q

(65)

Lecture 4: Storage Elements

•

Flip-Flop



Negative-Edge D Flip-Flop with synchronous reset

LIBRARY ieee;

USE ieee.std_logic_1164.ALL; ENTITY NDFF IS

END PDFF;

ARCHITECTURE RTL OF NDFF IS BEGIN

IF (clk’EVENT AND clk =’0’) THEN IF (rst_s = ’1’) THEN

q <= ’0’; ELSE

q <= d; END IF; END IF; END PROCESS; END NDFF;

d

q

(66)

Lecture 4: Storage Elements

•

Flip-Flop



Positive-Edge D Flip-Flop with asynchronous reset

LIBRARY ieee;

PORT (d, clk, rst: IN STD_LOGIC; q : OUT STD_LOGIC);

END PDFF;

ARCHITECTURE RTL OF PDFF IS BEGIN

PROCESS (rst, clk) BEGIN

IF (rst = ’1’) THEN q <= ’0’;

ELSIF (clk’EVENT AND clk =’1’) THEN q <= d;

END IF; END PROCESS; END PDFF;

d

q

(67)

Lecture 4: Storage Elements

•

Flip-Flop



Negative-Edge D Flip-Flop with asynchronous reset

LIBRARY ieee;

USE ieee.std_logic_1164.ALL; ENTITY NDFF IS

PORT (d, clk, rst: IN STD_LOGIC; q : OUT STD_LOGIC);

END PDFF;

ARCHITECTURE RTL OF NDFF IS BEGIN

PROCESS (rst, clk) BEGIN

IF (rst = ’1’) THEN q <= ’0’;

ELSIF (clk’EVENT AND clk =’0’) THEN q <= d;

END IF; END PROCESS; END NDFF;

d

q

(68)

Lecture 4: Assignment 3

• 32-bit ALU



Structural coding style



Using the 1-bit ALU developed in assignment 2



Using GENERATE statement



Write your own Testbench

ALU

a

b

sel

mode

cin

3

(69)

Lecture 4: Assignment 3

• 32-bit ALU



Structural coding style



Using the 1-bit ALU developed in assignment 2



Using GENERATE statement



Write your own Testbench