Elektronika Dasar Field Effect Transistor

3.Field-Effect Transistor (FET)

Junction Field-Effect Transistor (JFET)

n-channel JFET

V

GS = 0 V and VDS positive value

When VGS=0V and C some positive value,the upper region of the p-type material will be reverse biased higher than the lower region(the greater the reverse bias,the wider the depletion region).

As the voltage VDS is increased from 0 to a few volts,the current will increase as determined by Ohm’s law and The depletion region will widen,causing a noticeable reduction in channel widht.If VDS is increased to a level where it appears that the two depletion regions would “touch”, a condition referred to as pinch-off will result.The level of VDS that

establishes this condition is referred to as pinch-off voltage Vp (when VGS=0V and VDS>Vp IDSS). Input resistance > ₁₀8

VGS < 0V

Shockley’s Equation:

Voltage-Controlled Resistor:

where ro is the resistance with VGS _ 0 V and rd the resistance at a particular level of VGS.

p-channel JFET

PD = |VD|ID

Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) Or Insulated-Gate FET (IGFET)

When VGS=0V,the drain current is IDSS.

The negative potential at the gate will tend to pressure electrons toward the p-type substrate and attract holes from the p-type substrate.The drain current is therefore reduce with increasing negative bias for VGS.

The positive potential at the gate will draw additional electrons (free carrier) from the p-type substrate due to the reverse leakage current,reveals that the drain current will increase.

p-channel D-MOSFET

Enhachement-Type MOSFET (E-MOSFET) n-channel E-MOSFET

VT VGS(ON) VGS

VD(ON)

p-channel E-MOSFET

Complementary MOSFET (CMOS)

FET Biasing

For de analysis,the coupling capacitors are open cicuits. Fixed-Bias Configuration

Graphical Approach:

Self-Bias Configuration Graphical Approach:

Voltage-Divinder Biasing Graphical Approach:

Depletion-Type MOSFET

Graphical Approach:

Graphical Approach:

p-channel FET

V

_GS

=

V

_DS

=

V

_DD

−

I

_D

R

_D

=

12

V

−

I

_D

(

2

K

Ω)

I

_D

=

0

→

V

_GS

=

12

V

V

_GS

=

0

→

I

_D

=

6

mA

I

_DQ

=

2.75

mA

V

_GS

=

V

_DS

Graphical Approach:

→V_GS=V_G+I_DR_S=−4.55V+I_D(1 .8KΩ)

FET Small-Signal Model mS V mA V I g V V mS V mA V I g V V mS V mA V I g V V GS D m Q GS GS D m Q GS GS D m Q GS 4 . 1 1 . 1 5 . 1 5 . 2 4 . 2 75 . 0 8 . 1 5 . 1 3 . 3 6 . 0 2 5 . 0 = = D D = ® -= = = D D = ® -= = = D D = ® -= At At At D

I

D

V

GS

I

D

Output resistance:

FET ac equivalent model:

ID=IDSS

(

1−VGS

V_P

)

2

g_m=y_fs=ΔID

ΔV_GS|VDS=const=

2I_DSS

|V_P|

(

1−

V_GS

Input Impedance of the FET:

(the typical values: JFET

Output impedance of the FET:

r_d=ΔVDs

ΔI_D =

7V

0 . 5mA=14kΩ

Z_i(FET)=∞

¿

10

9

Ω

, MOSFET

≃

10

12

−

10

15

Ω)

Z_o(FET)=r_d= 1

FET Small-Signal Analysis Common-Source Circuit

Output resistance: FET ac equivalent model:

+VDD

+VDD

RD

C2

C1 R1

R2

Rs Cs

V = 0i Z = R ||ro D d

Z

_i

=

R

₁

||

R

₂

V

_o

=−(

g

_m

V

_gs

)(

R

_D

||

r

_d

)=−(

g

_m

V

_i

)(

R

_D

||

r

_d

)→

A

_v

=

V

o

+VDD

RG Rs

RD Vi d s o r V V -Io Vo D

r

_d

=∞

s

V

_gs

=

V

_i

−

g

_m

V

_gs

Ralignl

¿¿

_¿

¿

→

V

_i

=

V

_gs

(

1

+

g

_m

R

_s

)

¿

V

_o

=−(

g

_m

V

_gs

)

R

_D

¿

A

_v

=

V

o

V

_i

=−

g

_m

R

_D

1

+

g

_m

R

_s

¿¿

r

_d

≠∞

V_gs=V_i−I_oR_s I_o=g_mV_gs+Vo−Vs

r_d =gmVgs+

−I_oR_D−I_oR_s r_d

¿g_m(V_i−I_oR_s)+−IoRD−IoRs

r_d

→I_o=gmVi

1+g_mR_s+(RD+Rs)

r_d V_o=−I_oR_D=−gmRDVi

1+g_mR_s+(RD+Rs)

r_d

→A_v=Vo

V_i =− g_mR_D

1+g_mR_s+(RD+Rs)

Common-Drain (Source-Follower) Circuit

G S

Z_i=R_G

V_i=0→Z_o=R_S||r_d||1

g_m

Common-Gate Circuit

V_o=−(g_mV_gs)R_D=−g_m(−V_i)R_D→A_V=Vo

V_i=gmRD

Z_i=R_S||1

g_m

V_i=0→Z_o=R_D||r_d

Enhancemen MOSFET Amplifier

V_o=g_mV_gs(R_S||r_d)=g_m(V_i−V_o)(R_S||r_d)→A_v=Vo

V_i=

g_m(R_S||r_d)

2+g

2 ) ( ) ( )

( _{GS ON h}

ON D V V I k T

-= (typically 0.3 mA/V )2

V_o=(I₁−g_mV_gs)(R_D||r_d)=(Vi−Vo

R_G −gmVi)(RD||rd)

→A_V=Vo

Vi =

(1−g_mR_G)(R_D||r_d)

R_G+R_D||r_{d (for}

g

_m

R

_G

>>1

)

(for

R

G

>>

R

D _or

r

d

¿−gmRG(RD||rd)

R_G+R_D||r_d =−gm(RG||RD||rd)

¿−g_m(R_D||r_d)

I_i=Vi−Vo

R_G =

V_i(1−Vo

V_i )

R_G →Zi=

V_i I_i =

R_G

1−A_V = R_G

1−(−g_m(R_D||r_d))=

R_G

1+g_m(R_D||r_d))

V_i=0→R_D||r_d||R_G≃R_D||r_d

Bypassed Source Resistance

) || ( _{L D}

m i

o

V g R R

V V A = =

-Unbypassed Source Resistance

Common Gate

)

||

(

_{L D}

m i o

V

g

R

R

V

V