Chau high k metal gate conf foils 110603

Gate Dielectric Scaling for

High-Performance CMOS:

from SiO2 to High-K

Robert Chau

Intel Fellow

Technology and Manufacturing Group Intel Corporation

Content

• Introduction

• SiO2 Scaling

• Review on High-K Problems

• Significant Breakthroughs in High-K/Metal-Gate

• High-K/Metal-gate NMOS & PMOS Transistors with Record-Setting Drive Performance

Introduction

10 100

350n

m

250 n

m

180 n

m

130 n

m

90 n

m

Th

ic

kn

ess (

Å

)

• 1.2nm physical SiO2 in

production in our 90nm logic technology node

• 0.8nm physical SiO2 in our

research transistors with 15nm physical Lg

• Gate leakage is increasing

with reducing physical SiO2 thickness

• SiO2 running out of atoms

for further scaling

SiO2 Scaling

PolySi

Silicon PolySi

Silicon SiO2

Silicon substrate 1.2nm SiO ₂

Gate

Silicon substrate

1.2nm SiO₂

PolySi

Electrical Characteristics of

0.8nm Physical SiO2

0.0 0.5 1.0 1.5 2.0

-1 -0.5 0 0.5 1

Vg Capaci tance ( µF /c m ²) _NMOS PMOS NMOS PMOS --0.0 0.5 1.0 1.5 2.0

-1 -0.5 0 0.5 1

Vg (V) C apa ci tance (µ F /c m ²) NMOS PMOS NMOS PMOS 0.8nm 0.8nm Inversion Capacitance 0.0 0.5 1.0 1.5 2.0

-1 -0.5 0 0.5 1

Vg Capaci tance ( µF /c m ²) _NMOS PMOS NMOS PMOS --0.0 0.5 1.0 1.5 2.0

-1 -0.5 0 0.5 1

Vg (V) C apa ci tance (µ F /c m ²) NMOS PMOS NMOS PMOS 0.8nm 0.8nm 0.0 0.5 1.0 1.5 2.0

-1 -0.5 0 0.5 1

Vg Capaci tance ( µF /c m ²) _NMOS PMOS NMOS PMOS --0.0 0.5 1.0 1.5 2.0

-1 -0.5 0 0.5 1

Vg (V) C apa ci tance (µ F /c m ²) NMOS PMOS NMOS PMOS 0.8nm 0.8nm Inversion Capacitance 1E-6 1E-5 1E-4 1E-3 1E-2 1E-1 1E+0 1E+1 1E+2 1E+3

-1 -0.5 0 0.5 1

Vg (Volts)

Jg (A /c m ²) NMOS NMOS Inversion PMOS Inversion 1E-6 1E-5 1E-4 1E-3 1E-2 1E-1 1E+0 1E+1 1E+2 1E+3

-1 -0.5 0 0.5 1

Vg (Volts)

Research Transistor with 15nm

Physical Lg and 0.8nm Physical SiO2

0 100 200 300 400 500

0 0.2 0.4 0.6 0.8

Drain Voltage (V)

Dr ai n Cu rr en t ( µ A/µ m )

Vg = 0.8V

0.7V 0.6V 0.5V 0.4V 0.3V 15nm NMOS 0 100 200 300 400 500

0 0.2 0.4 0.6 0.8

Drain Voltage (V)

Dr ai n Cu rr en t ( µ A/µ m )

Vg = 0.8V

0.7V 0.6V 0.5V 0.4V 0.3V 15nm NMOS 1.E-08 1.E-07 1.E-06 1.E-05 1.E-04 1.E-03

0 0.2 0.4 0.6 0.8

Gate Voltage (V)

Drain Current (

A

/

µ

m)

Vd = 0.8V

Vd = 0.05V

S.S. = 95mV/decade DIBL = 100mV/V Ioff = 180nA/um 15nm NMOS 1.E-08 1.E-07 1.E-06 1.E-05 1.E-04 1.E-03

0 0.2 0.4 0.6 0.8

Gate Voltage (V)

Drain Current (

A

/

µ

m)

Vd = 0.8V

Vd = 0.05V

S.S. = 95mV/decade DIBL = 100mV/V Ioff = 180nA/um 15nm NMOS

0.8nm physical SiO2 0.8nm physical SiO2

M02 MCl₄(g)

Step 1

Step 2

MCl₄ + 2H2O(g) -> M02 + 4HCl(g)

Step 3

Step 4

Formation of High-K: Atomic Layer Deposition

M = Zr, Hf

Review on High-K Problems

(High-K/PolySi-Gate)

•

High-K and polySi gate are incompatible due

to Fermi level pinning at the high-K and

polySi interface which causes high threshold

voltages in transistors

•

High-K/polySi transistors exhibit severely

degraded channel mobility due to the

High-K and PolySi are Incompatible

O M

O O O O

M M M

O M

O O O O

M M M

O O O O O O O O

O M

O O O O

M M M

O M

O O O O

M M M

M

O M

O O O O

M M M

O M

O O O O

M M M

M Si

Si Si Si Si Si Si

Si Si

Si

Si Si Si Si Si Si Si Si Si Si Si

Si Si Si Si Si Si Si Si Si Si Si

Si Si Si Si Si Si Si Si Si Si

M Si

Si Si Si Si

Poly Si

Interface

High-K

M = Zr, Hf

Experimental Evidence of

Phonon Scattering in High-K

1.0E-05 1.5E-05 2.0E-05 2.5E-05 3.0E-05 3.5E-05 4.0E-05 4.5E-05

0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5

E-Field (MV/cm) d(1/ueff)/dT High-K/PolySi SiO2/PolySi Phonon scattering E-Field µ 0 1 > ∂ ∂ T PH µ 0 1 < ∂ ∂ T Coul µ 0 1 = ∂ ∂ T SR µ

µ_ph ↓ T ↑

µ_Coul ↑ T ↑

µSR~ const

Coulombic Phonon _Surface

Roughness

SR ph

Coul

eff µ µ µ

µ

1 1

1

Review on High-K Problems

(High-K/Metal-Gate)

•

Metal gate electrodes may be able to screen

the high-K SO phonons from coupling to the

inversion channel charge carriers and reduce

the mobility degradation problem

•

However the use of high-K/metal-gate

requires metal gate electrodes with the

“correct” work functions on high-K for both

PMOS and NMOS transistors for high

Significant Breakthroughs in

High-K/Metal-Gate made by Intel

•

N-type metal and P-type metal with the

correct work functions on high-K have been

engineered and demonstrated for

high-performance CMOS

•

High-K/metal-gate stack achieves NMOS and

PMOS channel mobility close to SiO2’s

•

High-K/metal-gate stack shows significantly

We have Engineered N-type and P-type Metal Electrodes on High-K with the “Correct” Work

Functions for NMOS and PMOS on Bulk Si

NDK

SDK

-1.1 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1

N+poly P+pol

y

P-metal

N-metal Metal A Metal B Metal C Metal D Metal E Metal F Metal G Metal H Metal I Metal J

Gate Electrode Materials

Transistor Flatband

Voltage

(V)

P-type Metal on High-K

N-type Metal on High-K

N+ PolySi/SiO2

P+ PolySi/SiO2

High-K/Metal-Gate Stack Achieves

NMOS Channel Mobility Close to SiO2

SiO2/polyS i

W fill + poor contacts

W fill + improved contact

Nitridation Optimizatio n

20Å High-K/polySi

TiN fill + improved contact

10 12 14 16 18 20 22 24 26

NMOS Mobility (cm

2 /V.s)

Eeff = 1.0MV/cm

High-K/Metal-Gate

High-K/Metal-Gate Stack Achieves

PMOS Channel Mobility Close to SiO2

10 15 20 25 30

Inversion Electrical Thickness, Toxe (Å)

PMOS Mobility (cm

2 /V.s)

High-K/Metal-Gate

SiO2/PolySi

High-K Reduces Gate Leakage

SiO2/polySi

High-K/metal-gate

1.E-04 1.E-03 1.E-02 1.E-01 1.E+00 1.E+01 1.E+02

0 5 10 15 20 25

Accumulation Electrical Tox [A]

Jox

[A/cm

High-K/Metal-gate NMOS and PMOS

Transistors with Record-Setting

Drive Current (Idsat) Performance

• NMOS and PMOS high-K/metal-gate transistors were made on bulk Si

– Physical gate length (Lg) = 80nm

– Electrical Oxide Thickness @ inversion (Toxe) = 1.45nm

• Very high NMOS Idsat

– Idsat = 1.66mA/um, Ioff = 37nA/um at Vcc = 1.3V

• Very high PMOS Idsat

High-K/Metal-Gate NMOS I

_on

- I

_off

0.8 1 1.2 1.4 1.6 1.8

1.0E-10 1.0E-09 1.0E-08 1.0E-07 1.0E-06

Ioff (A/µm)

Ion (mA/µ

m)

• Electrical Tox at inversion

(Toxe) = 1.45nm

• Vcc = 1.3V

High-K/Metal-Gate NMOS with Record-Setting

Drive Current Performance

• Electrical Tox at Inversion (Toxe) = 1.45nm • Transistor physical gate length (Lg) = 80nm

0 0.0002 0.0004 0.0006 0.0008 0.001 0.0012 0.0014 0.0016 0.0018

0 0.2 0.4 0.6 0.8 1 1.2 1.4 Vd (V)

Id

(

A

/µ

m

)

1.E-10 1.E-09 1.E-08 1.E-07 1.E-06 1.E-05 1.E-04 1.E-03 1.E-02

0 0.2 0.4 0.6 0.8 1 1.2 1.4 Vg (V)

Id

(

A

/µ

m

)

Ion = 1.66mA/um Ioff = 37nA/um

Lg = 80nm Toxe = 14.5A

Lg = 80nm Toxe = 14.5A

Vd=1.3V

High-K/Metal-Gate PMOS with Record-Setting

Drive Current Performance

1E-10 1E-09 1E-08 1E-07 1E-06 1E-05 1E-04 1E-03 -1.3 -1.1 -0.9 -0.7 -0.5 -0.3 -0.1 Vg (V) Id ( A /µ m ) Vd=0.05V Vd=1.3V

Ion = 693 µA/µm Ioff = 25 nA/µm

Lg = 80nm

Toxe = 14.5A

-7.E-04 -6.E-04 -5.E-04 -4.E-04 -3.E-04 -2.E-04 -1.E-04 0.E+00 -1.3 -1.1 -0.9 -0.7 -0.5 -0.3 -0.1 Vds (V) Id ( A /µ m )

Lg = 80nm

Toxe = 14.5A

Summary

• We have implemented 1.2nm physical SiO2 in our 90nm logic technology node and products, and have demonstrated 0.8nm physical SiO2

• We have engineered and demonstrated NMOS and PMOS high-K/metal-gate stacks on bulk Si with i) the correct work functions, ii) channel mobility close to SiO2’s and iii) very low gate leakage

• We have fabricated high-K/metal-gate NMOS and PMOS transistors on bulk Si with record-setting drive current performance