Tri gate conference foils 0603

Tri-Gate Fully-Depleted CMOS

Transistors: Fabrication,

Design and Layout

B.Doyle, J.Kavalieros, T. Linton, R.Rios

B.Boyanov, S.Datta, M. Doczy, S.Hareland, B. Jin,

R.Chau

Logic Technology Development

Outline of Presentation

•

Introduction

− Different Depleted Substrate Transistor (DST) Architectures

•

Experimental Results

•

Computer Simulation Results

− Dimensional Analysis

− Importance of Corner Effects

•

Tri-Gate Layout Analysis

Transistor Architectures

Single-Gate

Planar

L

Si H_Si

g

Si

Gate

Source Drain

~ Lg/3

Double-gate (e.g. FINFET)

W_Si L_g H_Si Isolation Gate 1 Gate 2 Source Drain

Tri-gate

Non-Planar

W_Si L_g H_Si Gate 1 Gate 2 Gate 3 Source Drain

Tri-gate Transistor

W_Si

L_g

Top Gate

Side Gate Side Gate

H_Si S/D D/S

Gate

Top Gate

Side Gate

Side Gate

Experimental Tri-Gate Process

•

Starting Si thickness = 50nm

•

BOX thickness ~ 200nm

•

Well implants

•

N

₂

O sacrificial oxidation

•

Physical Tox = 1.5nm

•

Poly thickness = 100nm

•

Raised source-drain

•

Nickel salicide

Top Gate

Side Gate

60nm NMOS Tri-Gate Transistors

1E-08 1E-07 1E-06 1E-05 1E-04 1E-03 1E-02

0 0.4 0.8 1.2

Vg (Volts) Id ( µ A/ µ m) Vd=0.05V Vd=1.3V 0.0E+00 2.5E-04 5.0E-04 7.5E-04 1.0E-03 1.3E-03

0 0.4 0.8 1.2

Id (A/µ m) Vg=1.3V Vg=1.1V Vg=0.9V Vd (Volts)

• Idsat = 1.23mA/µm and Ioff = 40nA/um at Vcc = 1.3V

• Subthreshold slope = 72mV/decade

60nm pMOS Tri-Gate Transistors

Gate Voltage (V)

Drain Curren t (A/ µ m) 0.E+00 1.E-04 2.E-04 3.E-04 4.E-04 5.E-04 6.E-04 -0.8 -0.4

Drain Voltage (V)

Drain Current (A/

µ m) 1E-09 1E-08 1E-07 1E-06 1E-05 1E-04 1E-03

-1.2 -0.8 -0.4 0

Vd=1.3V

Vd=0.05V

-1.2 0

• Idsat = 520 µA/um and Ioff = 24nA/um at Vcc = 1.3V

• Subthreshold slope = 69.5mV/decade

Double Gate-like

Understanding Tri-Gate Behavior

• Device simulator

- Full 3D single-carrier solution using DESSIS

device simulator

- Hansch quantum correction model applied - Intel 2.2 Ghz Xeon processor takes about 1

minute/bias point for an 18000 node mesh

• Simulated structures

- L_g=60 nm / H_Si=60 nm / W_Si=60 nm - L_g=30 nm / H_Si=30 nm / W_Si=30 nm - Electrical Tox varies from 22 to 34 A

Simulation of L

_g

=H

_Si

=W

_Si

=60nm

1.E-03

Vd=0.05V Vd=1.3V

DIBL=56 mV/V

S/S (0.05V)= 72.5mV/dec

S/S (1.3V)= 76mV/dec

1.E-04

1.E-07 1.E-06

Id (A)

1.E-05

1.E-08

1.E-09

0.0 0.3 0.6 0.9 1.2

Vg (V)

1.0E-03

Simulation of L

_g

=H

_Si

=W

_Si

=30nm

Vd=0.05V Vd=1.0V

DIBL=62 mV/V

S/S (0.05V)= 76mV/dec

S/S (1.3V)= 76mV/dec 1.0E-04

1.0E-05

1.0E-06

Id (A)

1.0E-07

1.0E-08

0.0 0.2 0.4 0.6 0.8 1.0

Vg (V)

Body Scaling Vs DST Architecture

Single-Gate

Double-Gate

Tri-Gate

0

10

20

30

H_Si=0.33*L_g

W_Si=0.66*L_g Lg =30nm

Lg =20nm

Lg =15nm

(H

si

, W

Si

(nm)

Minimum Body Dimension

Tri-Gate body size more relaxed than single-gate or

Tri-Gate Device Understanding

•

TCAD simulations partitioned

into 3 distinct regions:

Top channel

Sidewall channel

Corners

Components of Current

Vg (V)

Id (A/

µ

m)

1.0E-09 1.0E-08 1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02

0.0 0.2 0.4 0.6 0.8 1.0

Non-Corner Total

Corner Vd=1.0V

Vd=0.05V

non-Components of Current

0.0% 20.0% 40.0% 60.0% 100.0%

0.0 0.6

Vg (V)

% of Total Curre

n

t

Corner

Non-Corner

Vd=0.05V

Vd=1.0V

80.0%

0.2 0.4 0.8 1.0

Physics of Corner Device

R=8nm

Vg=0.5V, Vd=1.0V Cut at midpoint along channel

Proximity of the two gates at the corner give the nearly-ideal

Physics of Tri-Gate Device

hDensity 1E+18 1E+16 1E+14 1E+12 1E+10 1E+08 1E+06 10000 100 1 Top Gate Si Drain Lg =30nm TS i = 3 0 n m hDensity 1E+18 1E+16 1E+14 1E+12 1E+10 1E+08 1E+06 10000 100 1 Top Gate Si Drain Lg =30nm TS i = 3 0 n m Source hDensity 3E+04

(well conc. = 8E+18)

Importance of Corner Profile

1.E-12 1.E-10 1.E-08

0 0.2 0.4 0.6 0.8 1

Vg (V)

Corner Current (A/

µ

m)

R=0 nm R=5 nm R=10 nm R=15 nm R=20 nm R= infinity

Gate

Body

Body

Radius R

1.E-02

1.E-04

1.E-06

Layout Implications:

Fabricating Different Widths

Poly Fins

To meet different required widths for transistors,

Layout Considerations

Planar Transistor

Z_eff = Z

Tri-Gate Transistor

Fins

Z_eff = 0.6Z

For a given pitch, total current per unit layout-width of the Tri-gate transistor has only 0.60X the channel width of the standard transistor

Spacer-Defined Fins

Fins Fins

Zeff= 0.6Z

Oxide Blocks with nitride spacers

Z_eff= 1.2 Z

Litho-defined Fins _{For the same pitch, # of}

spacer-defined fins doubles that of litho-defined fins

Oxide blocks to define spacer-masks for

forming Si fins

Conclusions

• Tri-Gate transistors have been fabricated and achieve excellent drive current with near-ideal DIBL, S/S.

• Tri-Gate corners are responsible for the excellent sub-threshold slope, DIBL characteristics, as well as

relaxing the body dimensions compared to double-gate devices.

• In addition to the corners, the top-gate and sidewall channel regions are important in achieving optimal device performance.