03 Top Level View of Computer Function and Interconnection

Willia m St a llings Willia m St a llings

Com put e r Orga niza t ion a nd Arc hit e c t ure

a nd Arc hit e c t ure 8t h _{Edit ion}

Cha pt e r 3

Progra m Conc e ptg p

• Hardwired syst em s are inflexible

G l h d d

• General purpose hardw are can do

different t asks, given correct cont rol

i l

signals

Wha t is a progra m ?p g

• A sequence of st eps

h h l l

• For each st ep, an arit hm et ic or logical operat ion is done

Func t ion of Cont rol U nit

• For each operat ion a unique code is provided

provided

—e.g. ADD, MOVE

• A hardware segm ent accept s t he code and issues t he cont rol signals

Fe t c h Cyc ley

• Program Count er ( PC) holds address of next inst ruct ion t o fet ch

next inst ruct ion t o fet ch

• Processor fet ches inst ruct ion from

l i i d b C

m em ory locat ion point ed t o by PC

• I ncrem ent PC

—Unless t old ot herw ise

• I nst ruct ion loaded int o I nst ruct ion I nst ruct ion loaded int o I nst ruct ion Regist er ( I R)

• Processor int erpret s inst ruct ion and

Ex e c ut e Cyc ley

• Processor- m em ory

d t t f b t CPU d i

—Alt erat ion of sequence of operat ions —e g j um pe.g. j um p

I nt e rrupt sp

—e.g. overflow , division by zero

• Tim er

—Generat ed by int ernal processor t im ery p —Used in pre- em pt ive m ult i- t asking

• I / OI / O

—from I / O cont roller

• Hardw are failure

• Hardw are failure

I nt e rrupt Cyc lep y

• Added t o inst ruct ion cycle

h k f

• Processor checks for int errupt

—I ndicat ed by an int errupt signal

• I f no int errupt , fet ch next inst ruct ion

• I f int errupt pending:I f int errupt pending:

—Suspend execut ion of current program —Save cont extSave cont ext

—Set PC t o st art address of int errupt handler rout ine

—Process int errupt

M ult iple I nt e rrupt sp p

• Disable int errupt s

P ill i f t h i t t hil t —Processor will ignore furt her int errupt s whilst

processing one int errupt

I nt errupt s rem ain pending and are checked —I nt errupt s rem ain pending and are checked

aft er first int errupt has been processed

—I nt errupt s handled in sequence as t hey occur —I nt errupt s handled in sequence as t hey occur

• Define priorit ies

L i it i t t b i t t d b —Low priorit y int errupt s can be int errupt ed by

higher priorit y int errupt s

When higher priorit y int errupt has been —When higher priorit y int errupt has been

processed, processor ret urns t o previous int errupt

Conne c t ingg

• All t he unit s m ust be connect ed

ff f f d ff

• Different t ype of connect ion for different t ype of unit

—Mem ory

M e m ory Conne c t iony

• Receives and sends dat a

dd ( f l )

• Receives addresses ( of locat ions)

• Receives cont rol signals

I nput /Out put Conne c t ion(1 )p p ( )

• Sim ilar t o m em ory from com put er’s view point

view point

• Out put

—Receive dat a from com put er —Send dat a t o peripheral

• I nput

I nput /Out put Conne c t ion(2 )p p ( )

• Receive cont rol signals from com put er

S d l l h l

• Send cont rol signals t o peripherals

—e.g. spin disk

• Receive addresses from com put er

—e.g. port num ber t o ident ify peripheralg p y p p

CPU Conne c t ion

• Reads inst ruct ion and dat a

d ( f )

• Writ es out dat a ( aft er processing)

• Sends cont rol signals t o ot her unit s

Buse s

• There are a num ber of possible int erconnect ion syst em s

int erconnect ion syst em s

• Single and m ult iple BUS st ruct ures are m ost com m on

• e.g. Cont rol/ Address/ Dat a bus ( PC)

Wha t is a Bus?

• A com m unicat ion pat hw ay connect ing t wo or m ore devices

or m ore devices

• Usually broadcast

• Oft en grouped

—A num ber of channels in one bus

—e.g. 32 bit dat a bus is 32 separat e single bit channels

Da t a Bus

• Carries dat a

R b t h t t h i diff b t

—Rem em ber t hat t here is no difference bet ween “ dat a” and “ inst ruct ion” at t his level

Widt h i k d t i t f

• Widt h is a key det erm inant of perform ance

Addre ss bus

• I dent ify t he source or dest inat ion of dat a

C d d

• e.g. CPU needs t o read an inst ruct ion ( dat a) from a given locat ion in m em ory

• Bus widt h det erm ines m axim um m em ory capacit y of syst em

Cont rol Bus

• Cont rol and t im ing inform at ion

M d/ it i l —Mem ory read/ writ e signal —I nt errupt request

Big a nd Y e llow ?g

• What do buses look like?

P ll l li i it b d —Parallel lines on circuit boards —Ribbon cables

S i h b d —St rip connect ors on m ot her boards

– e.g. PCI

Single Bus Proble m sg

• Lot s of devices on one bus leads t o:

P t i d l

—Propagat ion delays

– Long dat a pat hs m ean t hat co- ordinat ion of bus use can adversely affect perform ance

can adversely affect perform ance

– I f aggregat e dat a t ransfer approaches bus capacit y

Bus T ype syp

• Dedicat ed

S t d t & dd li

—Separat e dat a & address lines

• Mult iplexed

—Shared lines

—Address valid or dat a valid cont rol line —Advant age - fewer lines

—Disadvant ages

Bus Arbit ra t ion

• More t han one m odule cont rolling t he bus

C d ll

• e.g. CPU and DMA cont roller

• Only one m odule m ay cont rol bus at one t im e

Ce nt ra lise d or Dist ribut e d Arbit ra t ion

• Cent ralised

Si l h d d i t lli b

—Single hardw are device cont rolling bus access

– Bus Cont roller – Arbit er

T im ingg

• Co- ordinat ion of event s on bus

S h

• Synchronous

—Event s det erm ined by clock signals —Cont rol Bus includes clock line

—A single 1- 0 is a bus cycle

—All devices can read clock line —Usually sync on leading edge

PCI Bus

• Peripheral Com ponent I nt erconnect ion

l l d bl d

• I nt el released t o public dom ain

• 32 or 64 bit

PCI Bus Line s (re quire d)( q )

• Syst em s lines

I l di l k d t —I ncluding clock and reset

• Address & Dat a

—32 t im e m ux lines for address/ dat a —I nt errupt & validat e lines

• I nt erface Cont rol

• Arbit rat ionArbit rat ion

—Not shared

—Direct connect ion t o PCI bus arbit erDirect connect ion t o PCI bus arbit er

PCI Bus Line s (Opt iona l)( p )

—Addit ional 32 lines —Tim e m ult iplexed

—2 lines t o enable devices t o agree t o use 64-g bit t ransfer

• JTAG/ Boundary Scan/ y

PCI Com m a nds

• Transact ion bet ween init iat or ( m ast er) and t arget

and t arget

• Mast er claim s bus

• Det erm ine t ype of t ransact ion

—e.g. I / O read/ w rit e

• Address phase

• One or m ore dat a phases

P

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B

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A

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Fore ground Re a dingg g

• St allings, chapt er 3 ( all of it )

d / f/ b / b /

• www.pcguide.com / ref/ m bsys/ buses/

• I n fact , read t he whole sit e!

• www pcguide com /