prep2002_new.ppt 207KB Jun 23 2011 12:30:50 PM

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09/14/17 1 Electronic Systems Design

Department of Electronics and Computer Science

University of Southampton,

UK

High-Level Synthesis

for On-line Testability

P. Oikonomakos and M. Zwolinski

Department of Electronics and

Computer Science,

University of Southampton

Hampshire SO17 1BJ

UK

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On-line testing

• flight/space electronics_{flight/space electronics}

• industrial/automotive electronics_{industrial/automotive electronics} • medical electronics_{medical electronics}

• deep submicron technologies_{deep submicron technologies}

 _{targets physical system failures}_{targets physical system failures}  _{detects them while system is}_{detects them while system is}

operating

 _{increases reliability in several}_{increases reliability in several} safety-critical applications,

safety-critical applications,

especially in hostile environments,

e.g.

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High-level synthesis

 _{the designer provides an abstract}_{the designer provides an abstract} specification of the

specification of the behaviour of his behaviour of his

conceptual design along with his

constraints and requirements

 _{the synthesis tool is responsible for}_{the synthesis tool is responsible for} producing an equivalent

producing an equivalent structural structural description

description

 _{high-level synthesis offers :}_{high-level synthesis offers :}

• fast time-to-market_{fast time-to-market}

• fast and efficient design space _{fast and efficient design space}

exploration

• efficient design optimisation at the _{efficient design optimisation at the}

highest level of abstraction

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On-line

testing

High-level

synthesis

High-level

synthesis for

on-line testability

 _{On-line testing resources will be}_{On-line testing resources will be} inserted

inserted automatically automatically by the tool by the tool when the designer requires them

when the designer requires them

 _{Comparing alternative testing}_{Comparing alternative testing}

techniques and choosing the most

appropriate in each particular case

will be facilitated.

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On-line testing techniques

 _{self-checking design}_{self-checking design}

 _{on-line built-in self-test (BIST)}_{on-line built-in self-test (BIST)}

 _{monitoring analogue characteristics}_{monitoring analogue characteristics}

 _{In this work, we focus on}_{In this work, we focus on}_self- self-checking design.

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Self-checking design

 _{CUT = Circuit Under}_{CUT = Circuit Under} Test

Test

 _{The CUT is augmented}_{The CUT is augmented} according to some

according to some error error detecting code

detecting code..

 _{Error detecting codes}_{Error detecting codes} include :

include :

• parity codes_{parity codes}

• duplication codes_{duplication codes}

• several others_{several others}

Augmented CUT

Checker

Error

 _{Duplication codes}_{Duplication codes}_{form the basis of}_{form the basis of} our technique.

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Duplication testing

 _{CUT* is functionally equivalent to CUT.}_{CUT* is functionally equivalent to CUT.}  _{Fault-secure by nature.}_{Fault-secure by nature.}

CUT CUT*

Comparator

Error

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Physical vs. Algorithmic

Duplication

Physical duplication Physical duplication

 _Opera_Opera_tors_tors_{(hardware modules) are}_{(hardware modules) are} physically duplicated

physically duplicated

 _{Results in more than 100% hardware}_{Results in more than 100% hardware} overhead

overhead

Algorithmic duplication Algorithmic duplication

 _Opera_Opera_tions_tions_{(functions) are}_{(functions) are} behaviouraly

behaviouraly duplicated duplicated

 _{Depending on circumstances, can}_{Depending on circumstances, can} result in significant hardware savings

result in significant hardware savings

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Inversion Testing

 _{INV(CUT) is the functional “inverse”}_{INV(CUT) is the functional “inverse”} of CUT.

of CUT.

Comparator

Error CUT

INV(CUT)

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Physical vs. Algorithmic

Inversion

Physical Inversion Physical Inversion

 _{Allied to physical duplication, has no}_{Allied to physical duplication, has no} advantage over it, therefore it is of no

advantage over it, therefore it is of no

interest

Algorithmic Inversion Algorithmic Inversion

 _{Allied to algorithmic duplication}_{Allied to algorithmic duplication}  _{Depending on circumstances, can}_{Depending on circumstances, can}

result in more hardware savings than

the algorithmic duplication technique

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Conclusions

and future work

 _{Our first experiments (using the}_{Our first experiments (using the}

MOODS

MOODS High-Level Synthesis Suite) High-Level Synthesis Suite)

have been encouraging.

 _{We are working towards automating}_{We are working towards automating}

the on-line test resource insertion

process, so that

process, so that no modification of no modification of

VHDL code will be required!!!

 _{Our system should be versatile}_{Our system should be versatile}

enough to recognise and apply the

most beneficial (duplication or

inversion) technique for each module

in a given design.

 _{Future steps include fault simulation}_{Future steps include fault simulation}

and investigating methods to test the

control path of our designs.