ATD press briefing IDF 091803

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Delivering Package

Innovations to Enable

Future Products

Delivering Package

Innovations to Enable

Future Products

Introducing the Industry’s First 90nm - Low K Organic Flip Chip Package

Introducing the Industry’s First 90nm

Introducing the Industry’s First 90nm -- Low K Low K Organic Flip Chip Package

Organic Flip Chip Package

Dan Belton & Johanna Swan

Assembly Technology Development

Assembly Technology Development

Technology Manufacturing Group

Chandler, Arizona

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2

Agenda

y

y Packaging @ IntelPackaging @ Intel

y

y Convergence… Changing the Role of Convergence… Changing the Role of Packaging

Packaging

y

y Packaging Challenges & Innovations Intel Packaging Challenges & Innovations Intel is Delivering

is Delivering

y

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Assembly Technology Development

Chandler Campus

The A ssem bly Technology

Research Lab… exploring

new assem bly capabilities

Pick & Place

Pick & Place

Dispense

W ire

Bonder

Printing

ATD’s main R&D facility located in

Chandler, AZ

Our Mission - Identify, Develop an Deliver Total

Interconnect Solutions to Meet Intel’s Business Needs

Our Mission

Our Mission -- Identify, Develop an Deliver Total Identify, Develop an Deliver Total

Interconnect Solutions to Meet Intel’s Business Needs

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4

Intel’s Global Packaging Development

Arizona Chandler

Flip Chip CPU Pathfinding & Development

Core Competency Base

Malaysia Penang*

Flip Chip Chipsets & Communications

Development

China Shanghai*

Wire Bond & Stacked Die Development

Philippines Cavite*

Wire Bond & Stacked Die Development

Japan Tsukuba

Stacked Package Pathfinding

California Folsom

Pathfinding

Distributed centers of excellence worldwide Distributed centers of excellence worldwide

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From Transistors to Systems

… Innovation in All Areas

From Transistors to Systems

… Innovation in All Areas

Package-to-Board Chip-to-Package

Board-to-System

Transistor-to-Transistor

Our Goal

Innovative, Efficient, High Performance, Low-cost Packages that Gives Intel

Silicon a Significant Competitive Advantage

Our Goal Our Goal

Innovative, Efficient, High Innovative, Efficient, High

Performance, Low

Performance, Low--cost cost Packages that Gives Intel Packages that Gives Intel

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Convergence… Changing

the Role of Packaging

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Convergence Driving

New Innovations

Convergence Driving

New Innovations

Demand

Demand

COMPUTING COMMUNICATIONS

Any Time, Anywhere, Any Device

Innovation

1985

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8

Integration via Silicon (SoC)

Power mgmt

Power mgmt

& peripherals

90nm Transistor Gate on 0.13µm Process

90nm

Logic

0.16µm2 _{Flash Cell} Flash Flash Cell Cell phone phone stds

stds..

S S R R A A M M Intel® Intel® MicroSignalMicroSignal _Arc h itecture Arc h itecture Flash+Logic

Density, Speed, & Power Consumption are Increasing… Packaging Must Adapt to Manage

Integration of New Features

Density, Speed, & Power Consumption are

Increasing… Packaging Must Adapt to Manage

Integration of New Features

Source: Intel

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Converged Devices Require

Mips & Mbit / milliwatt & millimeter3

Converged Devices Require

Mips & Mbit / milliwatt & millimeter3

y

y Combination of stacking Combination of stacking and integration required

and integration required

y

y x, y, z dimensions shrinkingx, y, z dimensions shrinking

y

y Bigger “M’s” and smaller Bigger “M’s” and smaller “m’s” are better

“m’s” are better

x

x yy

z z Computing

Computing

Communications

Memory

Convergence Increases Silicon Usage and Need for System in Package Solutions

Convergence Increases Silicon Usage and

Need for System in Package Solutions

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The Solution… Intel Brings it all Together

Architectural Changes to Silicon Design

Architectural Changes to Silicon Design

Enhance Package / Substrates

Enabling Technology on Motherboards

Novel Cooling & Power Delivery Solutions

System Integration & Enabling

System Integration & Enabling

Power Delivery Power Delivery

& Heat & Heat Removal Removal Systems

Systems

Packages

Motherboard Motherboard Silicon

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Packaging Challenges &

Innovations Intel is

Delivering

Packaging Challenges &

Innovations Intel is

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Packaging Challenges

1.

1. Industry Silicon & Package integration becomes Industry Silicon & Package integration becomes

more complex at 90nm and beyond

2.

2. Cooling complexity increasesCooling complexity increases

3.

3. Interconnect scaling needs novel approaches to Interconnect scaling needs novel approaches to

enable new product features

4.

4. Chip Scale Packaging Chip Scale Packaging -- SystemSystem--inin--aa--packagepackage

5.

5. The Road to Lead free The Road to Lead free

Goal : Bring technology innovation into High Volume Assembly at a Low Cost

Goal : Bring technology innovation into

High Volume Assembly at a Low Cost

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Silicon & Package Integration

More Complex

Silicon & Package Integration

More Complex

Inner Layer Dielectric StrengthInner Layer Dielectric Strengt

h

Time

y

y The Industry ChallengeThe Industry Challenge

y

y Circuit Signal Speed is impacted as silicon feature sizes are reCircuit Signal Speed is impacted as silicon feature sizes are reduced duced (delay is proportional to 1/RC)

(delay is proportional to 1/RC)

y

y TransitionTransition to Lower K dielectric materials is required to reduce to Lower K dielectric materials is required to reduce capacitance (charging delays)

capacitance (charging delays)

y

y Successful Integration of Low K Dielectric Material into SiliconSuccessful Integration of Low K Dielectric Material into Silicon & & Flip Chip Package Technologies requires a significant reduction

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Silicon & Package Integration

Solutions

Silicon & Package Integration

Solutions

Stress Reduction on Inner Layer

Stress Reduction on Inner Layer

Dielectric

Stress on I LD

Silicon Process Improvement Assembly Process Improvement Design & Materials Improvement

Stress Level on ILD too High

Existing

Technology _{Stress Level on ILD OK}_{Stress Level on ILD OK} Existing Process

New Process

Intel’s Assembly Technology Development Capabilities Enable Understanding and Integration of All Design,

Process and Materials Aspects

Intel’s Assembly Technology Development Capabilities

Enable Understanding and Integration of All Design,

Enable Understanding and Integration of All Design,

Process and Materials Aspects

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Introducing the Industry’s First

90nm Low K

Organic Flip Chip Package

Introducing the Industry’s First

90nm Low K

Organic Flip Chip Package

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1.

2.

2. Cooling complexity increasesCooling complexity increases

3.

3. Interconnect scaling needs novel approachesInterconnect scaling needs novel approaches

4.

5.

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Cooling

Total Package + System Solution Thermal Budget

Total Package + System Solution Thermal Budget

Temp – Silicon (T_j)

Temp – Package

Case (T_c) Temp – Ambient (T_a)

Temperature Gradient

Packaging

Provide Solutions for this interface

of the budget :

Smooth out Hot Spots

OEM Heat Sink Provide Solutions

for this interface of the budget

Integrated Thermal Solutions In The Package Reduce Heat Flux – Easier To Cool In The System

Integrated Thermal Solutions In The Package

Reduce Heat Flux

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Cooling Complexity Increases

Adjusting Material Formulation (filler size, loading, distribution) to Improve Thermal Conductivity

1 2 3

‘99 ‘01 ‘03

Package Thermal Resistance

Package Thermal Resistance

Continuing to Reduce Thermal Resistance by Optimizing Polymer Interface Material Fillers is an Industry Challenge

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Package

IHS (or Lid)

Die Thermal Interface

Material (TIM)

Back-Side Metal

Pb-Free Solder TIM

Heat Spreader Lid

Die

Lid Plating

WE ARE N

OW SHIPPI NG

Intel® Xe

on™ Proc

essors

Solder Thermal Interface Material

Introducing – Industry’s First High Volume Solder Thermal

Introducing

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Packaging Challenges

1.

2.

2. Cooling Complexity IncreasesCooling Complexity Increases

3.

3. Interconnect scaling needs novel approaches Interconnect scaling needs novel approaches to enable new product features

to enable new product features

4.

5.

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Package Interconnect Scaling

1999 2001 2001 2003 2005 I/O per mm

New Features Drive Higher Wiring Density

New Features Drive Higher

Wiring Density

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Package Interconnect Scaling

Flip Chip BGA

1.27 mm solder ball pitch

‘Balls Anywhere’ Pattern & Advanced Routing Design Increased I/O Capability 44%! 1.00 mm solder ball pitch

Increased I/O Capability 28% Increase!

Intel 845

Discrete MCH Single DDR Channel 593 Ball count/358 I/O

Intel 845G

Integrated Graphics Single DDR Channel 760 Ball count/368 I/O

Intel 865G/

Intel 865G/875P875P

Integrated Graphics Dual DDR Channel 932 Ball Count/529 I/O

WE ARE N

OW SHIPPI NG

Intel 865G

& 875P Ch

ipsets

Intel Maintained Constant 37.5 mm Package Size while Increasing

Intel Maintained Constant 37.5 mm Package Size while Increasing FeaturesFeatures

Enhancing Product Features While Maintaining

Packaging and Motherboard Technology Cost Structure

Enhancing Product Features While Maintaining

Enhancing Product Features While Maintaining

Packaging and Motherboard Technology Cost Structure

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Packaging Challenges

1.

2.

3.

4.

4. Chip Scale Packaging Chip Scale Packaging -- SystemSystem--inin--aa--packagepackage

5.

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Chip Scale Packaging Trends

y Chip Scale Package Pitch Reduction to .5mm (for those ready)

y Memory and System in Package y Stacked Die and Stacked Packages

y Last year we said they were coming

y Now they - ARE HERE

y Stacked Die… Was 2 Die, Went to 3 Die, Going to 4,5,6 Die

y Thin, thin, thin

y 2002 was .150 mm die

y Now Sampling in .075 mm die

y Tomorrow…. Less than that

Greater

Perform

ance, M

emory, C

omputin g

in smalle

r mm

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Integration via Packaging -

Thinning & Stacking

Integration via Packaging

-

Thinning & Thinning & Stacking Stacking 4 Die 4 Die Stack Stack

4 Die Stack with Large Overhang

But Challenges to Handling, Bonding, & Stacking

But Challenges to Handling,

Bonding, & Stacking

0% 20% 40% 60% 80% 100%

1 2 3 4 5 6 7 8 9

Number of Stacked Die

% T o t a l T h icknes s ( 1 .4mm M a x)

Thin Die Enables Thinner Packages

Thin Die Enables Thinner Packages Package Budget

Die Budget

Die Thinning and Stacking is Critical to Achieve SIP

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Introducing Ultra

Introducing Ultra--Thin Packaging (Intel® UTThin Packaging (Intel® UT--SCSP)SCSP)

2 Die

1.4mm Package Height

4 to 5 Die 1 to 1.2 mm 2 to 3 Die

1.2mm

8 Die Stack

>150 M Units Shipped

Intel® UT-SCSP

50 µm Die

75 µm Die Thinness

125 - 175 µm Die Thickness

• Extending the envelope with more die in less space

• 4 to 5 Die in 1mm to 1.2 mm Package Height

• High Volume Capability with High Reliability

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The Ultimate Flexibility

Introducing Intel® Folded Stacked Chip Scale Package

The Ultimate Flexibility

Introducing Intel® Folded Stacked Chip Scale Package

Introducing Intel® Folded Stacked Chip Scale Package

We Annou

nced in 2 00

We Would

Be Samp ling

E ARE NO

W SAMPL

ING 2 that

Industry’s First !! - Intel® Folded Stacked Chip Scale Package

A system in Package

W

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Logic

Logic -- Memory SystemMemory System--inin--aa--PackagePackage Several Flavors Being Developed Several Flavors Being Developed

Intel® Stacked Chip Scale Package (CSP)

SHIPPING

PXA261,

PXA262, PXA 263

Intel® Folded-SCSP

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Flip Chip in CSPs

Chip

Die Bumps Pkg Solder

Balls

Package Substrate Molded Plastic

FC-CSP with Exposed Die

Intel® Centrino™ with

Communication Die in Flip Chip CSP

Flip Chip Enables Flip Chip Enables

y

y Higher frequencies and R/F Higher frequencies and R/F performance

performance

y

y Reduction in package body sizeReduction in package body size

y

y Higher I/O in smaller chip areaHigher I/O in smaller chip area

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Packaging Challenges

1.

2.

3.

4.

4. Wireless packaging Wireless packaging -- SystemSystem--inin--aa--packagepackage

5.

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Industry Pb-free Challenges

y

y Reliability of Reliability of PbPb--free Solutions Across Industry at free Solutions Across Industry at Elevated Temperature

Elevated Temperature

y

y Capable at PbCapable at Pb--free Board Process Temp. (260C Pbfree Board Process Temp. (260C Pb--free vs 220C SnPb)free vs 220C SnPb)

y

y Compatibility of multiple solders in subCompatibility of multiple solders in sub--components in Pbcomponents in Pb--free board free board process

process

y

y PbPb--free Industry Infrastructure Readinessfree Industry Infrastructure Readiness

y

y Supply chain readiness Supply chain readiness ÆÆ100% BOM availability100% BOM availability

y

y Availability/ HVM capacity of Availability/ HVM capacity of PbPb--free components and materialsfree components and materials

y

y Management of conversion logistics and dualManagement of conversion logistics and dual--line (line (PbPb and and PbPb--free)free)

y

y PbPb--free Platform Costfree Platform Cost

Intel is Committed to Finding Appropriate and Cost-Effective Ways to Reduce Lead in its Products

Intel is Committed to Finding Appropriate and Cost

Intel is Committed to Finding Appropriate and Cost- -Effective Ways to Reduce Lead in its Products

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The Road to Pb-Free

y

y Several Several PbPb--free products are available and shipping free products are available and shipping today

today

y

y Intel certified its first PbIntel certified its first Pb--free product in October 2001 and free product in October 2001 and shipped its first Pb

shipped its first Pb--free product October 2002free product October 2002

y

y Packages include: Very Thin Profile Fine Pitch BGA (VF BGA), Packages include: Very Thin Profile Fine Pitch BGA (VF BGA), Intel® Stacked Chip Scale Package , P

Intel® Stacked Chip Scale Package , P--BGA BGA

y

y PbPb--free Second Level Interconnect development for free Second Level Interconnect development for Flip

Flip--Chip Packaging technology is underway Chip Packaging technology is underway y

y Focused on newer technologies under developmentFocused on newer technologies under development

y

y Reduction of Hazardous Substances (Reduction of Hazardous Substances (RoHSRoHS) compliant ) compliant product introductions will occur in phases

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Summary

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Summary

y

y Many Challenges are Being Met… Many Challenges are Being Met…

y

y Silicon/Package Integration… Transition to new dielectric materiSilicon/Package Integration… Transition to new dielectric materialsals

y

y Cooling Complexity… New products require better Interface MateriCooling Complexity… New products require better Interface Materialsals

y

y Interconnect Scaling… New features require more interconnectInterconnect Scaling… New features require more interconnect

y

y System in Package… Thinner Die and PackagesSystem in Package… Thinner Die and Packages

y

y Road to Lead Free… Intel is committed to the Industry Challenge Road to Lead Free… Intel is committed to the Industry Challenge

Intel’s Integrated Design, Silicon, Packaging Technology Development Enable the Delivery of Optimized Solutions

into High Volume

Intel’s Integrated Design, Silicon, Packaging Technology

Development Enable the Delivery of Optimized Solutions

into High Volume

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http://www.intel.com/research/silicon/packaging.htm

http://developer.intel.com/technology/itj/

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