Shiro IDF Tokyo 041103

(1)

Nanotechnology Fueling

Moore's Law

Koji Shiro

Director & General Manager

(2)

Outline

y

Key Messages

y

What is Nanotechnology?

y

Nanotech State of the Art

y

The Future

y

The Ultimate Vision

y

Summary

(3)

Key Messages

y Nanotechnology is here today in “state of the art” high speed Si CMOS process

technologies

y Si nanotechnology process

scaling/convergence will continue for the next 10-15 years

y Alternative new technologies have emerged and will begin to be integrated into Si CMOS by 2015

y Nanoscience research is needed to facilitate these radical new scalable technologies

(4)

What is Nanotechnology?

a. New structures like carbon nanotubes

b. Silicon devices made smaller

c. Arranging atoms and molecules

d. Letting atoms assemble themselves

e. Something far in the future

f. In production today

(5)

NSET* Nanotechnology

Definition (Feb 2000)

Research and technology

development at the atomic,

molecular, or macromolecular levels,

in the length scale of approximately

1 – 100 nanometer range

*

(6)

Silicon Nanotechnology is

Here!

10000 10000 1000 1000 100 100 10 10 10 10 1 1 0.1 0.1 0.01 0.01 Micron

Micron NanoNanometermeter-

-1970 1980 1990 2000 2010 2020

Nominal feature size

Nanotechnology Nanotechnology

130

130nmnm 90

90nmnm

70

70nmnm 50

50nmnm

Gate Width

(7)

Silicon Devices Shrink to

Virus Size

50nm _100nm

Influenza virus

Influenza virus

Source: CDC

Transistor for

90nm Process

Source: Intel

(8)

Moore’s Law In Action

1,000 10,000 100,000 1,000,000 10,000,000 100,000,000 1,000,000,000

1970 1975 1980 1985 1990 1995 2000 2005 2010 4004

8080

8086

8008

Pentium® Processor 486™ DX Processor

386™ Processor 286

Pentium® II Processor

Pentium® III Processor Pentium® 4 Processor

Heading toward 1 billion transistors in 2007

Itanium® Processor

>220

>220M Transistors Integrated Into M Transistors Integrated Into Devices Produced Today

(9)

>6 Orders Of Magnitude

Reduction in Cost/Transistor

0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10

'68 '70 '72 '74 '76 '78 '80 '82 '84 '86 '88 '90 '92 '94 '96 '98 '00 '02

$

Source: WSTS/Dataquest/Intel, 8/02

(10)

New Materials, Devices

Extend Si Scaling

Gate Gate Silicide Silicide added added Channel Channel Strained Strained silicon silicon

Changes

Made

Future

Options

High

(11)

New Materials, Devices

Extend Si Scaling

Source: Intel

Source: Intel

Metal lines

Al Cu Al Cu

Insulating

dielectric

SiO

SiO₂₂ SiOFSiOF CDO

CDO (low (low--k)k)

Changes

Made

Future

Options

Ultra Ultra Low

Low--kk Dielectric

Dielectric

Interconnects

(12)

The Future

y

Continue CMOS Nanoscaling

y

Non-classical CMOS

y

Convergence

(13)

Nanotechnology features

y

Structures measured in nanometers

–_{Less than 0.1-micron (100nm)}

y

New materials and device structures

–_{Incrementally changing silicon}

technology base

y

Materials manipulated on atomic

scale

–_{In one or more dimensions}

y

Increasing use of self-assembly

–_{Using chemical properties to form}

(14)

Intel Nano Transistors

90nm Node 2003 30nm Prototype (IEDM2000) 20nm Prototype (VLSI2001) 25 nm 15nm 15

15nm Prototypenm Prototype (IEDM2001) (IEDM2001) 65nm Node 2005 32nm Node 2009 Increasing leakage Increasing leakage 22nm Node 2011 10

(15)

Nanotechnology for Gate

Dielectrics

Integration is the key challenge

Integration is the key challenge

90

90nm processnm process 1X

1X

Experimental high

Experimental high--kk 1.6X 1.6X < 0.01X < 0.01X Capacitance Capacitance Leakage Leakage Silicon substrate Silicon substrate Gate Gate 3.0

3.0nm Highnm High--kk

Source: Intel Source: Intel

Silicon substrate

1.2

1.2nm SiOnm SiO₂₂ Gate

(16)

Lithography Gap to Close

with EUVL

1000 1000 100 100 10 10 ’

’8989 ’’9191 ’’9393 ’’9595 ’’9797 ’’9999 ’’0101 ’’0303 ’’0505 ’’0707 ’’0909 ’’1111 Initial Production

Initial Production

Feature size

157

157nmnm

13

nm (EUVL)

Lithography

Wavelength

193

193nmnm 248

248nmnm

Gap Gap

(17)

17

EUV LLC Consortium

Demonstrates EUVL

50

50nm Lines Printednm Lines Printed with EUV Lithography

with EUV Lithography

EUV

EUV LithographyLithography

Prototype Exposure Tool

EUV lithography is now in commercialization phase

EUV lithography is now

in commercialization phase

(18)

EUV Reflective Mask

Structure

_Conventional

optical photomask

13nm EUV light

Low Thermal Expansion Substrate

Absorber

Si

Si (~4.1nm)(~4.1nm)

Reflective

multi-layer coating 40 pairs Mo-Si

Mo (~2.8nm)

Buffer

λ

6” Fused silica substrate

λ

(19)

The Future

y

Non-classical CMOS

y

Convergence

(20)

Intel’s TeraHertz Transistor:

Lower I

off

Leakage

Raised

Raised

Source/

Drain

< 30

< 30nm Siliconnm Silicon OxideOxide Gate

Gate HighHigh--k k

Gate

Dielectric

(21)

Experimental Tri-Gate

Transistor

Source

Source

Drain

Gate

Source: Intel Source: Intel

Gate

Silicon

Drain

Source

y

Improved version of TeraHertz

transistor

– _{Better performance}

– _{Scalable to smaller sizes (low leakage)}

(22)

Nanotubes/Nanowires

( >> 2010?)

y Collaborations with universities in progress

y Good individual device data, many integration and materials issues to be resolved

Source: Morales &

Source: Morales & LieberLieber, Science , Science 279279, , 208 (1998)

208 (1998)

Silicon

Silicon NanowireNanowire Carbon

Carbon NanotubeNanotube

S D

(23)

The Limits of Logic Scaling

y

For an

arbitrary

switching device

made of of a single electron in a dual

quantum well

–_{Operating at room temperature}

y

It can be shown a power dissipation

limit of 200 W/cm**2

(24)

The Future

y

Non-classical CMOS

y

Convergence

(25)

Marriage of High Speed Logic

with Other Technologies

{

Today

y

Flash/DRAM

y

RF

y

MEMS/NEMS

y

Optoelectronics

y

Bioelectronics

y

Alternate memory

–_{MRAM, FeRAM, Ovonics}

{

(26)

Intelligent Silicon

E X P A N D IN G E X P A N D IN G EXTENDING MOORE

EXTENDING MOORE’’S LAWS LAW

Wireless Wireless Optical Optical Biological Biological Sensors Sensors Fluidics Fluidics Mechanica Mechanicall

Nano

Silicon Innovation Enabling Convergence

Silicon Innovation Enabling Convergence Silicon Innovation Enabling Convergence

Expanding

Expanding the Silicon the Silicon CanvasCanvas

Nano

Nano is is HereHere New

New DevicesDevices, ,

Materials

Materials, and , and ProcessesProcesses

SSI

SSI LSILSI VLSIVLSI Discrete

(27)

The Future

y

Continue CMOS nanoscaling

y

Non-classical CMOS

y

Convergence

(28)

Novel Devices:

R+D Time Requirements

y Product development spectrum – _Software

– _System – _Assembly – _mArch

– _{Power delivery and cooling} – _{Circuit Design}

– _Layout

– _Processing – _Materials

y Change that affects one level or two adjacent levels is relatively easy to manage Î 2-5

years R+D effort

y Change that affects many levels is very difficult Î 6 – 20 years R+D effort

(29)

Emerging Research Architectures

ATURITY

~2009?

(30)

Technical criteria

y

CMOS compatibility

y

Energy efficiency

y Scalability y Performance

y Architectural compatibility

y Sensitivity to parametric variation y Room temperature operation

y Stability and reliability

Option Must Be Superior to

Option Must Be Superior to Si Si CMOS Based CMOS Based On Cost, Power, Performance

(31)

The Ultimate Vision

The brain is the

ultimate model for its ability to deal with

complexity

y Little understanding on its architecture & organization

y Compared to tomorrow’s computers

– _{Orders of magnitude more powerful} – _{Self assembled}

– _{Parallel operation}

– _{Self repairing to a significant degree} – _{Fault tolerant}

(32)

Summary

y Nanotechnology is here today in “state of the art” high speed Si CMOS process

technologies

y Si nanotechnology process

scaling/convergence will continue for the next 10-15 years

y Alternative new technologies have emerged and will begin to be integrated into Si CMOS by 2015

y Nanoscience research is needed to facilitate these radical new scalable technologies