Chapter 4
the reflection at the input of the amplifier, the input return loss need not be especially low.
4.3 Principles of LNA Design
When designing a low-noise amplifier, both the signal and noise performance must be considered. We saw in Section 2.2 that the noise waves emanating from the different ports of a microwave device can be correlated. The key to designing low- noise amplifiers is to reflect some fraction of the noise wave emanating from the input back into the device with the appropriate phase shift such that it cancels out part of the noise wave emanating from the output (Haus and Adler 1958). The complex reflection coefficient that must be presented to the transistor to achieve this effect is referred to as Γopt. Figure 4.1 shows a plot of Γoptfor the transistors used in the LNA.
It can be seen that a simple 4.3 nH inductor at the gate comes close to noise-matching the transistor in the 4-8 GHz band. The figure also shows that there is a trade-off between designing for optimum signal performance or minimum noise.
The most critical aspect of a low-noise amplifier (aside from the transistors) is the tuning circuit at the input of the first FET. When designing this component, the signal performance is often considered to be secondary to the noise performance.
After the input to the first stage of the amplifier has been designed for minimum noise, subsequent stages of the amplifier are tuned to equalize the gain. Matching the output to some particular impedance (in this case, 50 Ω) is normally easy, and is accomplished by connecting a resistor of the appropriate size from the drain of the last transistor to an RF ground. This is important to minimize standing waves on transmission lines connected to the output of the device.
The stability of the amplifier against oscillations must be considered both in and out of band up to the highest frequencies at which the transistors still have appreciable gain. The amplifier can oscillate if the input or the output has reflection gain. Since the reflection at a port depends upon the impedance presented to it, it is desirable to design the amplifier to be unconditionally stable, i.e., stable against oscillations for
Figure 4.1 Transistor input reflection Γopt for optimum noise performance. The solid blue curve is the reflection coefficient that, when presented to the input of the FET, would give the lowest possible noise temperature, while the dotted green curve shows the reflection coefficient that would impedance-match the input of the FET. The dashed red curve is the reflection coefficient presented by a 4.3 nH inductor. Note that while Γoptis moving counterclockwise as the frequency increases from 4 to 8 GHz, the inductor reflection coefficient is moving clockwise. This 50 Ω impedance Smith chart is a polar plot of the reflection coefficients: the center corresponds to no reflection (i.e., a matched load), while the outer circle corresponds to total reflection. The phase of the reflection starts at zero at the right side of the polar plot (an open circuit), and increases counterclockwise.
all passive source and load impedances.
4.4 A Single-Ended Quasi-Monolithic Amplifier
Normally, when a low-noise amplifier with a good input match is needed, a balanced design is used (Padin and Ortiz 1991). With this approach, two amplifiers are com- bined in parallel with 90◦ hybrids (four port devices used to introduce 90◦ phase shifts) such that the reflections from the two parallel stages add 180◦ out of phase and cancel themselves out. This frees the designer to match the transistors for mini- mum noise. Balanced designs work well for moderate bandwidths up to a little over an octave; beyond that, it becomes difficult to make good hybrids. Unfortunately, balanced designs have a few drawbacks. Having two amplifiers in parallel would in- crease the thermal load on the cryostat, and the extra input circuitry adds loss, which increases the noise temperature. Because of these drawbacks, we chose to use a sim- pler single-ended design and put an isolator at the input to prevent standing waves.
The isolator, like a 90◦ hybrid, adds loss that increases the overall noise temperature, but the single-ended amplifier only generates about half the waste heat of its balanced equivalent, and is easier to design, build, and fabricate.
The initial reason for considering using a MMIC was to gain better control over parasitics compared to a discrete-component amplifier. However, fabrication of MMIC devices is expensive due to tiny features in the transistors. Choosing a quasi-MMIC approach not only greatly reduces the fabrication costs, it also permits the selection of transistors from known good wafers. The relative ease of assembly associated with the QMMIC devices was also attractive, and bump-bonding the transistors creates a robust circuit free from wire bond parasitics. Other advantages of the QMMIC approach include small size and relatively easy adaptability to different packaging constraints. For example, the QMMIC amplifier could more easily be integrated into the mixer block of an SIS receiver than a discrete-component amplifier.
The transistors are 160 µm gate InP HEMTs provided by the Microwave and Lidar Technology Section at the Jet Propulsion Laboratory. The transistors were measured two ways. Some transistors were measured directly with a microwave probe sta- tion and network analyzer. Others were bump-bonded to simple coplanar waveguide (CPW) substrates, and probed including some length of CPW line. The measured scattering matrices of the bump-bonded transistors were mathematically deembed- ded from the CPW lines to arrive at measured scattering matrices for bump-bonded transistors. It was found that the differences between the bare and bump-bonded transistors were small.
Marian Pospieszalski’s FET model (Pospieszalski 1989) was fit to the measured data using the SuperMix optimizer to determine the model parameters, see Sec- tion 2.7. The noise prediction from the model, given a best-guess value of 430 K for the noisy drain-resistor temperature, was used without any direct measurement of the transistor noise parameters.
4.6 Design and Simulations
Different tuning circuits for the amplifier were evaluated by first designing them to noise-match 50 Ω to Γopt at the band center, then using SuperMix to optimize the designs across the full band for flat gain above 30 dB, low noise, input reflections below about -10 dB, output reflections below -25 dB, and unconditional stability at all frequencies. During this initial design phase, efforts were made to keep the total power consumption low by minimizing resistive elements in the drain current path.
The final design chosen for layout used inductive tuning at the transistor gates, some source inductance for stability, gates biased through large resistors (large enough to not couple appreciable noise into the gate), and resistively biased drains.
After the ideal circuit designs were completed, physical resistors, capacitors, and inductors were laid out. The substrate includes air bridges and a resistive layer, but
Layer Thickness
Bump Gold 8µm
Air Bridge Gold 1µm
Air 2µm
SiN 296 pF/mm2
Gold 1µm
NiCr Resistor 50 Ω/square
GaAs 250 µm
Table 4.1 Layers of the QMMIC Substrate
for ease of fabrication does not include via holes. Each component, including the spiral inductors, was simulated with Agilent’s Momentum electromagnetic (EM) field simulator (Agilent Technologies). Results of the EM simulations were saved as scat- tering parameter files, which were then imported back into SuperMix for the final simulation. At this point, the predicted results including field simulations differed enough from the original design that the amplifier was re-optimized, and the com- ponent layouts modified accordingly. Two designs were selected for fabrication, one optimized for best performance (Figure 4.2), and one optimized for greater stability.
The final simulation is listed in Appendix F. The predicted gain and noise are shown in Figure 4.3.
The DC gate and drain bias lines for each transistor were kept separate to reduce power consumption on the cryogenic stage and allow the performance to be fine- tuned. Each gate bias line starts with a voltage divider before passing through an RC filter network. By dropping the gate bias voltages by a factor of 10, the dividers both protect the transistors and reduce the effects of noise on the bias lines. RC filter networks are also used on the drain bias lines.
4.7 Mask Layout
The layers of the QMMIC substrate are shown in Table 4.1, and the layout is shown in Figure 4.4. The substrate is gold-backed 250 µm GaAs. The input is coplanar waveguide (CPW) at the left edge of the chip. From left to right, the signal passes
49
290 pH
RF In
50Ω
50Ω Ω
190
50Ω
50Ω Ω
190
50Ω
150Ω
50Ω Ω
190
10 pF 290 pH
1.8 nH 290 pH
6.5 nH
130 pH
Vd1
1.1 nH
30 pF 10 pF
1 K 27 pF
Vg1
1.6 K
12 pF
27 pF
130 pH
Ω Ω
Vd3
130 pH
Vd2 Vg2
40 pF 68 43
10 pF 1 K 27 pF
1.6 K
39 pF
27 pF 12 pF
10 pF 1 K 27 pF
1.6 K
12 pF
27 pF
Ω RF Out
Ω 30
200