Figure 6.1 shows a cross section of a PMOSFET fabricated in a modern technology as well as a three-dimensional TCAD PMOSFET with features similar to the one shown in Figure 6.1a. The parasitic bipolar device can be seen between the source (emitter), n-well (base), and drain (collector). In the transistor’s off-state, the drain is grounded and the source and n-well are biased high (typically at whatever VDD for the technology happens to be). From the point of view of the parasitic bipolar device, the base/collector junction is reverse-biased while the emitter/base junction sees the built-in potential of the junction.
During an ion strike of sufficient intensity to a n-well, for example, the electric field
(a) (b)
Figure 6.1: (a) Cross section of a modern PMOSFET device showing the parasitic bipolar device between the drain, substrate, and source and (b) a typical MOSFET device showing the well contact. Both after [64].
around the strike is significantly reduced and the generated electrons are swept out of the well through the well contact. The flow of electrons through the well leads to a potential gradient along their current path to the well contact (due to the current moving through some finite well resistance to the contact) [58]. This potential gradient could result in a drop in potential near the channel of the PMOSFET. Lowering the potential near the channel is synonymous with lowering the built-in potential barrier at the parasitic bipolar device’s emitter/base (source/n-well) junction. If the barrier is sufficiently lowered, the source can begin to inject holes into the well, which can be collected by the reverse-biased n-well/drain (base/collector) junction. This is a charge-enhancement effect commonly referred to as the parasitic bipolar effect, which can cause the drain to collect additional charge, beyond that which it would have collected had the parasitic bipolar device not turned on. This can be a significant concern for PMOSFET devices fabricated in an n-well over a p-substrate. It is less of a concern for NMOSFETs fabricated in a p-well over p-substrate, as the electrons generated by the ion strike are not confined to the well, and are free to move deeper into
the substrate as well as to any nearby well contacts. This limits their ability to significantly modulate the well potential.
Previous work concerning WPM effects has focused primarily on device-level or mixed- mode simulations to study the device response of individual transistors during WPM events [58, 62, 64, 69, 70], circuit-level measurements to examine the effects of WPM on circuit response [65, 83, 84], or a combination of the two. Much of the device-level simulation work focuses on ions with LET values less than 10 MeV-cm2/mg (however, at least one study has examined device-level WPM effects in a triple well technology for a 40 MeV- cm2/mg ion [70]). Also, many of the available device-level studies utilize device-level simulations as opposed to experimental measurements. This is because WPM effects have been primarily studied in the context of small devices fabricated in advanced technology nodes. It can be difficult to determine the transient SE response of such devices experimen- tally. Their small size makes device-level experimental measurements difficult.
While simulations provide valuable insight into the device-level response during WPM events, experimental measurements of individual device response (e.g., through high-speed transient capture) could further develop the understanding of WPM events.
As stated earlier, many device-level WPM studies focus on lower LET ions. Higher LET ions have been used in circuit-level studies. One such study examined the circuit- level effects attributed to WPM for LETs as high as 100 MeV-cm2/mg [62]. The high LET values in that study corresponded to an effective ion LET due to changing the ion angle of incidence. The actual ion LET was approximately 60 MeV-cm2/mg. Further- more, the metric studied was single-event transient pulse width in an inverter chain, which, while valuable for a circuit-level study, does not necessarily provide insight into the current transient response of a single device as a result of WPM. However, device-level simulations were used to describe the benefits of guard bands and high-density well contacting schemes for reducing WPM effects.
This work provides a device-level experimental study of WPM effects following a high-
LET ion strike. To do this, a large-area PMOSFET device was fabricated in an n-well over a p-substrate. While a large device will not experience the parasitic bipolar charge collection enhancement described earlier (do to its long channel length), it will still be susceptible to the effects of a significantly modulated well potential. This work uses backside TPA and broadbeam heavy-ion measurements along with device-level TCAD simulations to exam- ine the influence of modulating the well potential on the overall device response. Device- level current transients exhibiting WPM effects are shown, and their origin is described.
Specifically, significant WPM can lead to a transient change in the junction capacitance.
For the large junctions used here, this can produce a measurable current transient. Also, TCAD simulations show that the WPM following a high-LET heavy-ion strike is sufficient, in some cases, to lower the source/well potential barrier, which could cause the source to inject holes into the well.