List of Tables
6.1 Design and fabrication of all-Nb SIS mixers
good impedance matching to low-resistance tunnel junctions, large area junctions between 1.2 J.Lm2 (RN rv 17 0) and 2.3 J.Lm2 (RN rv 9 0) can be designed making usc of JPL's all-optical-lithography junction fabrication process. Higher-resistance submicron junctions could be fabricated using electron-beam lithography, but the processing is more difficult, and the smaller devices can be more sensitive to static discharge. In addition, large-area devices are less susceptible to saturation from higher-intensity sources. One drawback of large junctions is the need for higher LO power, which scales directly with the total junction area. This can pose a problem at high frequencies, when strong LO power is not available, as will be shown later.
During the design stages, the most uncertain parameters arc the junction specific capacitance and the junction area that will be achieved in a given fabrication run. To allow for parameter variation, three different nominal junction sizes were included for each tuning circuit design. The tuning circuit for each frequency band was designed for a junction area of 1.7 J.Lm2 and an assumed specific capacitance 85 fF / J.Lm2. The same tuning circuits were used on junctions with sizes of 1.2 J.Lm2 and 2.3 J.Lm2. So for the middle design, the junction would have a normal state resistance of 11.8 0 and a capacitance of 140 fF.
A different tuning circuit was designed for each of the 450, 550, 650, and 750 GHz frequency bands. The design method optimized the rf coupling efficiency from the antenna to the tunnel junction resistance in the frequency range of interest, as dis- cussed in chapter 4. For microstrip lines, the thickness of the Nb conductor films was assumed to be 200 nm. The insulation SiO layer had a nominal thickness of 200 nm for the center inductor but 400 nm for the transformer sections. The devices all utilized a 2.5 J.Lm length of microstrip (with the width and thickness equal to those of the inductor) to connect the last transformer section with the inductor section. The insulation thickness around the junction was limited to about 200 nm because a thicker one would make the self-aligned lift-off technique difficult. The thicker insula- tion layer of the transformer sections helped to increase the characteristic impedance of the microstrip line. The width of the inductor was fixed at 5 ftm. Optimiza-
Table 6.1: Assumed parameters in all-Nb mixer design junction RNA product 20 D-1-Lm:l
junction size 1.7 !-Lm2
junction specific capacitance 85 fF
1
1.Lm2 SiO thickness for the inductor 200 nm SiO thickness for the transformer 400 nm SiO dielectric constant € = 5.6€oNb film thickness 200 nm
Nb gap voltage Vgap at 0 K 2.9 mV Nb critical temperature Tc 9.2 K Nb normal state resistance at Tc 5 1-LD-cm physical temperature of the device 4.2 K
tion variables included the length of the inductor and the widths and lengths of the transformers. For all-Nb mixers, two sections of transformers were used.
The PCIRCUIT program was then used to optimize the tuning circuits in a fre- quency bandwidth of 100 GHz (e.g., 400 - 500 GHz for the 450 GHz band). To summarize, the assumed parameters used in the design are given in Table 6.1, and the optimized microstrip widths and lengths are listed in Table 6.2. The calculated characteristic impedance and effective wavelength of the designed inductor and trans- former microstrip lines at the center frequencies are presented in Table 6.3.
The mixer chips were fabricated at the JPL Center for Space Microelectronics Technology, using the standard Nb/ Al-oxide/Nb trilayer process (LeDuc et al. 1987).
First the trilayer was deposited in situ onto a 50 mm diameter, 0.25 mm thick high- resistivity silicon wafer. The ground plane and the slot antennas were defined with standard optical lithography and lift-off. Secondly a layer of 200 nm SiO film was deposited by thermal evaporation. The junctions were then defined by optical lithog- raphy and formed by reactive ion etching (RIE). Thirdly, an extra layer of 200 nm SiO was deposited on the appropriate area to produce a total SiO thickness of 400 nm for the impedance transformer. The transmission lines were then made out of a 0.2 /-Lffi thick Nb layer. Finally, the contact pads for the IF connectors and de bias supply
Table 6.2: Designed parameters for the all- 1b SIS tuning circuits
microstrip parameters 450 GHz 550 GHz 650 GHz 750 GHz (width x length, J..Lm2) device device device device Inductor (between jet. centers) 5.0 X 23.5 5.0 X 14.9 5.0 X 9.8 5.0 X 6.9 1st transformer section 2.0 X 51.9 2.0 X 45.9 2.0 X 37.7 5.8 X 15.0 2nd transformer section 4.6 X 62.3 4.7 X 50.7 4.5 X 41.1 3.3 X 15.0
Table 6.3: Characteristic impedance and effective wavelength of the designed mi- crostrip lines given in Table 6.2 at the designed center frequency
characteristic impedance device device device device
& effective wavelength 450 GHz 550 GHz 650 GHz 750 GHz
inductor Zo 7.8
n
7.9n
8.on
8.3n
inductor Aeff 216 J..Lm 175 J..Lm 145 J..Lm 121 J..Lm 1st transformer Z0 21.2
n
27.4n
27.8n
11.1n
1st transformer Aeff 259 J..Lm 210 J..Lm 176 J..Lm 148 J..Lm 2nd transformer Z0 13.8
n
13.6n
14.3n
19.1n
2nd transformer Acff 252 J..Lm 204 J..Lm 171 J..Lm 146 J..Lm
were covered with gold for easy contacting. The whole wafer was diced into 1.2 mm x 1.5 mm individual mixer chips. A picture of a single mixer chip is shown in Fig. 6.1.
For this batch of mixer fabrication, it was found through tlw usc of the test die on the device wafer that the undercut in the junction dimensions wa.c;; ,...__ 0.2 J..Lm. The junction specific capacitance was ,...__ 85 fF / J.Lm2 as determined by FTS tests discussed
in next section.