Figure 4.6: Gate-sourceI-V characteristics for two G-GO devices. (a) Data from a G-GO FET (tgo= 4 nm) recorded in helium atmosphere at room temperature (solid line) and 1.4 K (dashed line).
The device was fabricated using a low-temperature process to bake the PMMA used for electron beam lithography. (b) Data from a G-GO capacitor (tgo 4 nm) recorded at room temperature (solid line) and 4.2 K (dashed line). The latter curve has been multiplied by 100 for visibility. The device was fabricated using the “standard” recipe for PMMA-based electron-beam lithography.
Figure 4.7: Gate conductance vs. temperature for two G-GO devices. Both devices were made using the “standard” recipe.
oxide occurs via a thermally activated process.
Gate conductance for two “standard”-recipe devices is plotted on a log scale againstT1{4 in Figure 4.7. The linear decrease oflnpGtgqdown to 10 K is consistent with a variable-range hopping model. The leakage current in this case is therefore unlikely to be related to the theoretical band gap [88] of GO in a straightforward way.
4.3.2 Breakdown electric field
Graphite oxide’s breakdown electric field was measured by slowly increasingVtguntilItgshowed a sharp jump, indicating irreversible damage. Data from a relatively thick device (tgo35 nm) mea- sured atT = 10 K are shown in Figure 4.8. At 3.5 V the gate conductance became unstable, finally showing a large jump at 3.8 V. Thereafter the gate current followed a higher curve, identified by the downward pointing arrow, indicating dielectric breakdown. G-GO FETs can typically withstand stresses of greater than1–3108V/m at room temperature, compared with109V/m for bulk SiO2(e.g., [89]). With experience, one is able establish safe limits for the top-gate voltage for each device based on only the measured thickness (using atomic force microscopy) of the graphite oxide.
Approximately 10 devices were fabricated using the “standard” process and 20 devices using the low-temperature process. A significant fraction were found to have top-gate shorts, possibly caused by errors in lithography alignment or undetected pin-holes in the graphite oxide. Adopting
Figure 4.8: Dielectric breakdown of the GO layer in a G-GO FET
Table 4.1: Maximum applied gate stress for several G-GO transistors tgo(nm) Vmax(V) Emax(V/m)
4 1.3 3.1108
10 1.0 1.0108
18 4.2 2.3108
35 3.5 1.0108
a layer-transfer process to obtain more uniform graphite oxide or a self-aligned top-gate would probably improve the yield. Safe top-gate voltage limits were established as part of measuring each fully functional FET, and are listed in Table 4.1. The actual breakdown electric field is likely to be slightly higher than these values.
4.3.3 Estimation of dielectric constant
After establishing a safe range of top-gate voltage, the source-drain resistance of each G-GO FET was measured using low-frequency lock-in techniques while sweeping Vtg and back-gate voltage Vbg. The resulting resistance versusVtgandVbgdata for a device withtgo= 18 nm, taken atT= 1.4 K with zero magnetic field, is shown in as a color-scale plot in Figure 4.9a. There is a pronounced resistance peak along the diagonal of the plot combined with a nearly horizontally oriented peak at approximatelyVbg = 35 V, similar to that found in previous reports [67, 90–97]. These peaks can be understood by considering the schematic representation of the device shown in Figure 4.10. Regions 1 and 3 are not covered by the local top-gate and are therefore doped by only the back-gate. Region 2, however, couples significantly to both gates. A simple model for the resistance is given as
Rµ1 (
L2{W Cbg1 Vbg Ctg1 Vtg
L1 3{W Cbg1 Vbg
)
(4.1)
whereL2is the length of region2,L1 3is the combined length of regions1 and 3,W is the sample width, andCbg1 ,Ctg1 are the back and top-gate capacitances per unit area, respectively; the mobility µis assumed to be constant across all three regions andVbgandVtgare defined relative to the charge neutrality condition where all regions have zero doping.
Thus, sweeps at constantVbg, shown in Figure 4.9b, have a single peak (attributable to the first term in equation 4.1) which shifts position withVbg. Sweeps at constantVtg, shown in Figure 4.9c,
Figure 4.9: Two terminal resistance as a function of top-gate voltage and back-gate voltage atB= 0 andT = 1.4 K. (a) Color plot showing independent doping of channel regions1 –3 and 2. (b) Hor- izontal data slices at constant back-gate voltage, withVbg indicated by color-coded arrows placed at the upper edge of (a). (c) Vertical data slices at constant top-gate voltage, withVtgindicated by color-coded arrows placed at the right edge of (a)
have one main peak corresponding to the Dirac point of regions1 and 3 plus another peak which may occur above, below, or at the same value ofVbg depending on the contribution of the top-gate.
The relative capacitance of the top and back-gates can be calculated by considering the denominator of the first term of equation 4.1, which is equal to the charge density in region2. WhenRis at a local maximum, as on the diagonal resistance peak in in Figure 4.9a, this charge density approaches zero, yielding the relationship
Ctg1 Cbg1
Vbg Vtg
. (4.2)
Figure 4.10: Schematic representation of a G-GO FET. The graphene channel, contacted at one end by source biasVsand by drain biasVd, is divided into three numbered regions defined by the edges of the top-gate.
Given tox = 290 nm, ϵox = 3.9ϵ0, and tgo = 18 nm, the slope of this peak indicates graphite oxide’s relative dielectric constant κ 4.3. Thus, the top-gate may generate a carrier density of 51012cm−2while remaining below the breakdown field of graphite oxide mentioned above, which is sufficient for applications such as analog electronics [98]. Note that the quantum correc- tions toCtg1 andCbg1 were not included in this analysis.4