7.4 Theoretical analysis
7.4.2 FEM Model
Figure 7.26: Schematic of model used to simulate the behavior of a dual gate diode.
The model used for the simulation can be seen in figure 7.26. It has axial symmetry and the carriers are confined to the bright green core in the middle of the structure. The white region is the thermal oxide that has been grown on the silicon nanopillar while the cross-hatched regions show the area of the oxide underneath the gates. The gate voltage is applied at the outside boundary of the oxide and the source and drain voltages are applied at the top and bottom boundaries of the silicon core as seen in figure 7.27.
For the device under simulation it was assumed that the bandgap was at 2 eV [20] and that due to both depletion and low dopant concentration, the Fermi level sits in the middle of the bandgap.
The expressions used to calculate the carriers induced by the gate potential are:
n=NCexp
Ef−Ec kT
, p=NVexp
Ev−Ef kT
(7.13)
where NC,V = (2.51×1019cm−3)(m∗n,p/mo)3/2for bulk silicon. We use these numbers in our case for
Figure 7.27: The biasing scheme for the simulation.
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simplicity; for a more exact model these will have to be recalculated to take into account the lack of the six fold degeneracy of the conduction band. The finite element model applies the gate voltage, uses the resultant potential distribution to find the distance between the Fermi level and the band edges, calculates the local concentration of carriers and then uses this concentration to modify the original potential distribution. This process is repeated until a stable potential/carrier distribution is obtained. Figure 7.28 shows a potential distribution for +/- 1V applied to the gates and the source and drain fixed at 0 V. The built-in potential, calculated from the shape of the potential in the silicon core, is about 1.7 V.
Figure 7.28: Potential distribution for Vg = +/- 1V and Vs = Vd = 0V. The z-axis goes from the bottom to the top of the page and the r-axis from left to right
Figure 7.29 shows the unit charge density under the previously mentioned biasing scheme. Note that the applied gate voltage is modified to take into account the flat-band voltage from trapped charges so that carriers are induced evenly on either side of the junction.
Plotting the carrier density with respect to the outline of the device (figure 7.30) shows that, under an applied bias of 0 V, the carriers are concentrated between the gate and source or gate and drain.
Since this device is effectively a ‘PN’-type device the dominant current comes from minority
Figure 7.29: Potential and carrier distribution for Vg = +/- 1V and Vs = Vd = 0V.
Figure 7.30: Carrier distribution for Vg = +/- 1V and Vs = Vd = 0V. The arc-length in this case is taken at r = 0 and goes from the drain to the source or z = 0 to the height of the structure (200 nm).
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carrier diffusion. Unfortunately carrier diffusion was left out the simulated model, to be added in a future version of the simulation. However it was still possible to estimate the current under forward and reverse bias by examining the change in carrier concentration under different source- drain voltages. Since there were no efforts made to create sources and sinks of charges, excess charges were swept to the electrodes and gathered; so long as the excess charge concentration was several orders of magnitude less than the effective ‘doping’ concentration, the excess minority carriers did not perturb the potential distribution or doping and the device behaved similar to a PN diode.
Figure 7.31 shows the carrier distribution with Vg = +/- 1V and Vs = Vd = 0V (blue) or Vs = -Vd
= 1 V (green). The inset shows the excess, minority, hole concentration at the right hand, ‘n-type’
region of the device. The minority carrier density is calculated by integrating the total number of excess carriers (holes in the example) and dividing by the volume of the region where the carriers are in the minority; in this case the n-type region.
Figure 7.31: Carrier concentration at forward bias (green) vs. zero bias (blue). The arc-length in this case is taken at r = 0 and goes from the drain to the source or z = 0 to the height of the structure (200 nm). The inset shows the excess holes found at the drain electrode in the n-type region under forward bias. The arc-length in this case goes from the left to the right side of the dotted box.
Figure 7.32 shows a log-plot of the excess carrier concentration found in the FEM model for various applied biases. An exponential is fit to the linear region of the plot and has the form
∆np= ∆pn = 4.353×10−38exp(Va/kT). Following the trend presented inAllen et al.[93] we make
Figure 7.32: Log-plot of the excess minority carrier concentration for Vg = +/- 1V under forward bias (green squares). The blue line is an exponential fit to the linear portion of the excess carrier concentration. For simplicity, the applied voltage is split evenly between the source and drain; Vs
= -Vd = Va/2.
the assumption that the diffusion length of electrons and holes is equal to the shortest dimension in the silicon core, in this case Ln = Lp ∼3 nm. Assuming that the electron and hole recombination time is 1 ns we get diffusion constants of Dn = Dp = 9×10−9m2/s. We can calculate the total current as:
Itot(Va) =qA Dn
Ln
∆np(Va) +Dp Lp
∆pn(Va)
(7.14) where both ∆np and ∆pn are calculated from the simulation and given by the green squares in figure 7.32. Plotted in 7.33 is the simulated current under forward bias. The blue line represents the current calculated from the fit in figure 7.32 and the red squares are the current calculated directly from the FEM simulation.
We can see that the current reaches high level injection at above 2 V of forward bias or roughly as the applied voltage reaches the value of the built-in potential. The leakage current under reverse bias is on the order of 3×10−27 A, a somewhat non-physical number. However this fits with the simple model under investigation that does not take into account any tunneling or recombination effects which greatly increase the leakage current. Recent work[95] has shown that SWNT ambipolar devices that can passµA of forward current have leakage currents in the pA range.
In order to estimate the number of photons generated from such a device we assume a quantum efficiency of 0.1%, a reasonable number given a total carrier recombination time of 1 ns and published radiative recombination time of about 100-200 ns [20]. This corresponds to roughly 10 million
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Figure 7.33: Linear and log plot of the I-V relationship under forward bias for a simulated ambipolar LED. The red squares are the results of the simulation and the blue line is from the best-fit curve in 7.32. Note that under greater forward power the simulation begins to diverge from the best fit line and decrease its slope. This is at roughly the point where the applied source-drain voltage approaches and exceeds the buil-in voltage. The equations (based on the Boltzman approximation) used to estimate the carrier distribution are no longer valid as the band-bending results in the fermi level crossing into both the conduction and valence band.
photons generated each second; for an emission wavelength of 600 nm the output power is in the pW range. However we can excite several thousand to million of these pillars at once by patterning over arrays of pillars instead of single pillars to directly increase the output power for a given applied voltage and current.