Chapter 7: Selective Growth of PECVD Graphene on Cu Nanostructures
7.4 Future Work
semiconductor industry has developed and proposed using Co or Ru as an alternative metal to solve the issues in the interconnect.146 Demonstration of a low-temperature PECVD growth of graphene uniformly on other metal but not on low-k dielectrics is also worth to explore the possibility to continue Moore’s Law.
Figure 7.7 (a) SEM images (b) AFM images and (c) Raman spectra of graphene on semiconductor industrial wafers under different growth conditions. First row: before growth.
Second row: 1min growth time. Third row: 2min growth time. Fourth row: 10 min growth time with graphite protection
C h a p t e r 8
CONCLUSION
We have developed different methods in the synthesis of graphene and graphene-based nanostructures on a variety of substrates by means of PECVD techniques. The graphene synthesis includes horizontal growth of SLG and MLG sheets, vertical growth of graphene nanostructures such as graphene nano-sheets and GNSPs with large aspect ratios, and direct and selective deposition of MLG on nanostructures. The rich chemical environment provided by PECVD enables graphene growth on a range of different material surfaces at lower temperatures and faster growth than typical thermal CVD growth. Additionally, proper choices of the precursor and source gases can simplify the graphene synthesis into a single-step process, provide control of the aspect ratios, and even induce desirable functionalities in the samples. Therefore, PECVD techniques for graphene synthesis are highly versatile and also promising for large-scale industrial applications.
We have also demonstrated a new approach to manipulating the topological states in single layer graphene via nanoscale strain engineering. By placing strain-free single layer graphene on different architected nanostructures to induce global inversion symmetry breaking, we are able to induce giant pseudo-magnetic fields, realize global valley polarization, and achieve periodic one-dimensional topological channels for protected propagation of chiral Fermion modes in strained graphene. Non-local resistance and non- local magnetoresistance are measured on both strained and unstrained graphene devices, which confirm strain-induced valley Hall effect (VHE), the occurrence of quantum valley Hall effect (QVHE) at the Dirac point at low temperatures, and the presence of pseudo- magnetic field-induced quantum oscillations by nanoscale strain engineering. The methodology presented in this work not only provides a new platform for designing and controlling the gauge potential and Berry curvatures in graphene but is also promising for realizing scalable graphene-based valleytronic devices.
A p p e n d i x
RGA Spectra of PECVD Single-layer Graphene Growth
Figure A1. (a) RGA spectra of CH4 partial pressure in the growth chamber as a function of time. (b) ~ (e) Optical images showing the change of the backside of Cu foils at different times.
One interesting feature to determine the success of graphene growth I found is the CH4
partial pressure recorded in the RGA spectra. Fig. A1(a) is three representative RGA spectra of CH4 partial pressure, where the shade band indicates the time interval from turning on to off the plasma. The black curve is a reference spectrum of CH4 partial pressure where no Cu foil is inside the tube. Because CH4 was cracked into smaller radicals in the plasma environment, the CH4 partial pressure dropped when plasma was on. When we put Cu foil into the tube, CH4 partial pressure changes dramatically as shown in the blue curve and red curve, where the blue curve represents an unsuccessful graphene growth and the red curve represents a successful growth. As we mentioned in Chapter 3, Cu etching always accompanies successful graphene growth. We also always found there is a peak increase at the beginning of CH4 partial pressure when Cu starts to etch, as indicated in the green circle on the red curve. On the contrary, no such peak was seen in the blue curve when no or very little Cu etching. Next, when the graphene synthesis process is finished, there is a sudden increase of CH4 partial pressureas shown in the yellow circle on the red curve. Fig. A1(b) ~ (e) is optical images of the backside of the Cu foil at different times during the growth, as denoted by the arrows in Fig. A1(a). Cu oxide and Cu were etched from Fig. A1(b) to (c), revealing fresh Cu surface. As graphene keeps growing on the backside and more Cu is deposited to the holder, Cu darkens with time.
Silicon Substrate Cleaning The silicon substrate was purchased from Siltronix. It’s covered with 300 nm dry-thermal oxide. The silicon is P-type Boron doped and 500µm thick. The crystal orientation is (100) and resistivity is 0.001 ~ 0.005 ohm-cm. Before any process, the silicon substrate is first sonicated in acetone and IPA, followed by an RCA clean and DI rinse. The detailed cleaning process is as follows:
1. Sonicate the Si substrates with acetone, isopropyl alcohol, and deionized water
2. RCA-1 clean
Prepare RCA-1 bath: 5 parts of deionized water + 1 part of 29% ammonia water (NH3) + 1 part of 30% hydrogen peroxide (H2O2)
Soak wafer in RCA-1 bath at 75°C for 10 minutes Rinse with DI water and blow-dry
3. RCA-2 clean
Prepare RCA-2 bath: 6 parts of deionized water + 1 part of 27% hydrogen chloride (HCl) + 1 part of 30 % hydrogen peroxide (H2O2)
Soak wafer in RCA-1 bath at 75°C for 10 minutes Rinse with DI water and blow-dry
Graphene transfer
PMMA transfer
PMMA 950 A4 is spin-coated on the graphene/Cu foil at 4000 rpm for 1 minute. Then the sample is baked at 180ºC for 1 minute to evaporate the solvent. The bottom side of graphene (without PMMA protection) is etched for 1 minute in an RIE oxygen plasma at 10 sccm, 20 mTorr, and 80W. The PMMA/graphene/Cu foil is then put on top of the 0.2 M ammonium persulfate ((NH4)2S2O8) to etch Cu foil. A plastic spoon or glass slide is then used to scoop PMMA/graphene film and place it into a DI water bath for ~ 10 minutes to rinse the remaining ammonium persulfate residues. This rinsing process is repeated for three times to fully remove any residues. Finally, the PMMA/graphene is scooped up by the target substrate. Usually there is some water trapped between the graphene and substrate. The sample is left at room temperature to evaporate the trapped water gradually. After PMMA/graphene film fully attached to the substrate surface. The sample is baked out at ~ 50 ºC overnight to completely remove the water and graphene can be better adhesive to the substrate. PMMA is then removed in acetone overnight.
Polymer free transfer
This method is modified by a polymer-free transfer method147 without using two syringe pumps. Similar to the PMMA transfer, graphene/Cu foil is placed on top of the Cu etchant solution, which is mixed with IPA and 0.1M ammonium persulfate. The setup is shown in Fig. A1. A glass protective holder was used to locate graphene and prevent it from attaching to the edge of the petri dish. Four glass pillars were used to fix the position of the glass protective holder from moving around. After Cu foil is etched, one pipette was used to slowly removed the etchant. Another pipette was used to slowly inject mixed DI water/IPA (10:1) solution to rinse the graphene sheet. This process is repeated three times. Finally, the target substrate is put underneath the floating graphene in the DI water/IPA solution. The solution is slowly removed by a pipette to land the graphene onto the substrate. The sample was then baked out using the same method mentioned in the PMMA transfer.
Figure A2. (a) Setup of the polymer-free transfer method. Graphene/Cu foil was placed in a glass protective holder. (b) After Cu foil was etched by (NH4)2S2O8
Device Fabrication
Electron Beam Lithography
The 495 A4 PMMA is spin-coated on the chip at 3000 rpm for 1 minute and baked for 1 minute. Graphene Hall bar and TLM sample are patterned by 30keV electron beam lithography with NPGS on the Quanta 200F in Kavli Nanoscience Institute. The chip is then dipped in a 3:1 volumetric ratio of isopropanol (IPA) and methyl isobutyl ketone
(MIBK) for 60 secs and then Immediately transfer to 100% IPA for 60 seconds to dilute away MIBK. The chip is blown dry by N2. Graphene without PMMA protection is then etched using an RIE oxygen plasma at 10 sccm, 20 mTorr, and 80W for 30 seconds. PMMA is then removed in acetone overnight. The chip is then baked out in the forming gas (Ar:
H2 = 10: 1) at 350 ºC for 1 hour to remove any PMMA residues.
SiO2 nano-cone array fabrication process
Figure A3. SiO2 nano-cone array fabrication process.
1. Si chip with a 300 nm oxide layer was ultra-sonicated in acetone and IPA for 10 min respectively and then blown dry with nitrogen.
2. Spin coat ~ 100 nm PMMA on the SiO2 and bake on a hot plate at 180 °C for 1 minute.
3. Using typical E-beam lithography method to pattern disc arrays 4. Deposit 15 nm Ni
5. Lift off the resist by soaking the chip in acetone overnight.
6. Use C4F8/O2 reactive ion etching (RIE) to create SiO2 nano-pillars.
7. Dip the chip in a buffered oxide etch (BOE) for ~ 20 seconds until Ni discs fall off.
Figure A4. SEM images of (a) Ni nanodiscs on a Si substrate. (b) Ni/SiO2 nanopillars after C4F8/O2 (RIE) for 30s. (c) BOE etch for 13s. (d) BOE etch for 20s until Ni discs fall off, showing SiO2 nanocones.
Deposit Ti/Au Contacts
Contacts are patterned by 30keV electron beam lithography with NPGS on the Quanta 200F. Bilayer resist is used to here to have a better lift-off process. The chip is spin-coated by PMMA 495 A4 at 4000 rpm for 1 minute and baked for 1 minute. The second layer is spin-coated by PMMA 950 A4 at 4000 rpm for 1 minute and baked for 1 minute. The chip is then followed by a typical electron beam lithography process.
The contacts are deposited using a Lesker Labline e-beam evaporator. In order to have a better contact resistance, it’s required to deposit metal in lower pressure. Before transferring the chip into the main chamber, we deposit 10 nm Ti at 1Å/s as a titanium sublimation pump and the pressure can usually reach 3 × 10-8 torr. After transferring the chip into the main chamber, 5nm Ti at 0.5Å/s followed by 100nm Au at 1Å/s are deposited.
Once the contacts have been deposited, the chip is soaking in acetone overnight. It’s then sprayed with acetone and IPA to remove lift-off Au and then blown dry with N2.
Wire Bonding
A wire bonder West Bond model 7476D-79 is used to bond Al wires from the sample contacts to the pads on a PC Board. It’s found that we need to use low power to bond the wire on the sample contacts without punching through the material and shorting to the underlying Si back gate. The typical recipe I used is ultrasonic power 150 and ultrasonic time 25ms on the sample contacts.
Figure A5 Optical image of samples after wire bonding.
Dielectrophoresis method for aligning graphene nanostrips
Dielectrophoresis method has been widely used in aligning carbon nanotubes (CNTs).148–
150 This method has been discovered to work on CNTs in (IPA) and CNTs move toward both electrodes and align along the electric field. Follow similar ideas, we report the alignment of GNSPs with the use of the AC dielectrophoresis method. This method is
performed by the following steps: (1) GNSPs on Cu foil samples are immersed in 1,2- DCB solvent for 20 hours to peel off GNSPs from the Cu foils, and the suspension is then sonicated for 3 minutes to break down big chunks of GNRs. (2) We patterned several electrodes (1µm wide) with 2.5 µm spacing. These thin electrodes were between two bigger electrodes which were used for applying an AC electric field to align GNSPs. (Fig. A6(a)) (3) The suspension is dropped by micropipette onto the Au electrodes. An AC electric field with frequency varies from 50 kHz to 500 kHz and voltage slowly ramping up to 60V is applied to the big electrodes until 1,2-DCB has evaporated. (Fig. A6(b))
Figure A6 (a) Au electrode pattern for GNSPs alignment and electronic transport measurement. (b) AC electric field is applied to the big electrodes with two Tungsten tips.
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