IDEAL TRANSMISSION-LINE FUNDAMENTALS
3.5 TRANSMISSION-LINE REFLECTIONS
3.5.5 Lattice Diagrams for Nonideal Topologies
will give a total magnitude at the source endvB=va+vb+vc=0.8+0.8+ 0.16=1.76 V, with the reflected portionvcof 0.16 V traveling toward the load.
This process is repeated until the voltage reaches a steady-state value of 2 V. If the same procedure is applied to the falling edge of a digital waveform, the signal integrity of a digital pulse propagating on this system can be calculated, as shown in Figure 3-31c. Notice how the reflections give the waveform a “stair-step”
appearance at the receiver (node B), even though the unloaded output of the voltage source is a square wave. This effect occurs when the source impedance (Rs) is larger than the characteristic impedance (Z0) and is referred to as an underdriven transmission line.
Example 3-5 Multiple Reflections for Rs < Z0 When the characteristic impedance of the transmission line is greater than the source impedance, as shown in Figure 3-32a, the reflection coefficient looking into the source will be negative:
source= 25−50 25+50 = −1
3
When the lattice diagram is solved, as shown in Figure 3-32b, it is easy to show that a negative reflection at the source will produce a “ringing” effect.
This is known as anoverdriven transmission line. The resulting distorted digital waveform is shown in Figure 3-32c. Since the procedure for solving the lattice diagram is identical to Example 3-3, the exercise is left to the reader.
0
z
0 l
t
1.33 V
250ps 2.66 V
1.77 V 2.22 V
1.92 V
1.33 V
−0.443 V
−0.443 V 0.148 V 500ps
750ps 1000ps
2.07 V (b)
vs 25 Ω
50 Ω B
A
(a) 0-2 V
Γs
td= 250 ps
Γt
−1
0 1 2 33 4 5
1 2 3
Time, ns (c)
Volts
Waveform at B Waveform at A
Figure 3-32 (a) Example of an overdriven transmission line; (b) lattice diagram; (c) dig- ital waveform.
reflected, as governed by the reflection coefficient (3-102) looking into line 2 from line 1,
2=Z02−Z01 Z02+Z01
and part of the signal (vb) will be transmitted, as governed by the transmission coefficient, as defined in equation (3-103):
T2= 2Z02
Z02+Z01 =1+2
Γ4
0
vB
va
vA′
vB′
Γ1 Γ2Γ3
T2 T3
td
4td 3td 2td
vc vb
vd ve
vf vg
vh vi
vC vs
Rs Rt
l1 z01
l2 z02
Figure 3-33 Lattice diagram for two cascaded transmission lines with different impedance values and identical lengths (l1=l2).
Figure 3-33 also depicts how a lattice diagram can be used to solve for multiple reflections on a transmission-line system with a series of transmission lines with more than one characteristic impedance. Note that the transmission lines in this example are of equal length (l1=l2), which simplifies the problem because the reflections from each section will be in phase. For example, in Figure 3-33, the transmitted portion of ve adds directly to the reflection, vf. When the two transmission lines are of different lengths, the reflections from one section will not be in phase with the reflections from the other section, which complicates the diagram drastically. When the signal reaches the termination, the reflection is governed by the reflection coefficient looking into the termination resistance at the load (4):
4= Rt−Z02
Rt+Z02
The portion of the signal reflected off the termination resistor will travel back toward the source and experience another reflection when it reaches the junction between transmission lines,
3= Z01−Z02 Z01+Z02
where3is the reflection looking into line 1 from line 2. Part of the signal will be reflected back toward the load as calculated by3and part transmitted toward the source, as dictated by the transmission coefficientT3:
T3=1+3
The portion of the signal transmitted through the junction toward the source will experience another reflection when it arrives atRs:
1=Rs−Z01
Rs+Z01
The signal will subsequently bounce back and forth between the source and the termination load until equilibrium is reached. The voltage levels are calculated in the same manner as the single-line lattice diagram with a little more accounting.
The initial voltage launched onto the line is va=vs
Z01 Z01+Rs
and the voltage levels of the reflections on the line are vb=vaT2
vc=va2
vd=vc1
ve=vb4
vf =vd2+veT3
vg=ve3+vdT2 vh=vf1
vi=vg4 giving source-side voltages of
vB =va+vc+vd
vC =va+vc+vd+vf +vh and load voltages of
vA =vb+ve
vB =vb+ve+vg+vi
where the remaining reflections are left for the reader to calculate.
Multireceiver Topologies So far in this book we have covered many issues that deal with an interconnect connecting two components. However, this is not always the case. Often, it is required that a single driver be connected to two or
Receiver 2 Receiver 1
00 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
0.5 1 1.5 2 2.5
Time, ns
Volts
vs
0-2 V Rs = Z0
l1 z01
l2 z02 l2 = l3
z02 l3
Figure 3-34 Signal integrity of a T-topology when the leg lengths and characteristic impedances are equal.
more receivers. In these cases, the topology of the interconnect can affect system performance dramatically. For example, consider Figure 3-34, which is a case where one driver is connected to two receivers. In this example, the impedance of the base (Z01) is equal to the impedance of the two legs (Z02), and the legs are of equal length (l2=l3). When the signal propagates to the junction, it will see an effective impedance ofZ02/2, resulting in the waveform in thefigure that steps up toward thefinal value in the same manner as an underdriven transmission line as calculated in Example 3-4. When the impedance of the legs is twice that of the base (Z02=2Z01), the effective impedance the signal will see at the junction will be equal to the base, so that no reflections are generated.
When the structure is unbalanced, as in the case where one leg is longer than the other, the signal integrity will deteriorate dramatically because the reflections will arrive at the junction at different times. To gain an intuitive understanding of how the multiple reflections from different legs interact, it is useful to solve a multiple-legged lattice diagram at least once, which is demonstrated in the following example.
Example 3-6 Calculate the first few reflections of the unbalanced T-topology shown in Figure 3-35 assuming thatZ0=Rs =50,l1 andl3 are lengths that corresponds to a propagation delay of 250 ps, andl2 has a delay of 125 ps.
SOLUTION Referring to the lattice diagram in Figure 3-35, thefirst and sec- ond vertical lines represents the electrical pathway between the driver and the junction, the third vertical line represents the pathway between the junction and the end of the short line (receiver 1), and the fourth vertical line represents the
vs
0-2 V Rs = Z0
z0 l1
Receiver 2 Receiver 1 l2
z0
z0 l3
Γ5
Γ4
Γ1 Γ2Γ3
T3 T2 0
250ps
500ps 750ps
1000ps
a a
b y
a
g A
B b
c d e f
Figure 3-35 Lattice diagram of a T-topology when the leg lengths are not equal.
end of the long line (receiver 2). The initial voltage step launched onto line 1 is vi =vs
Z0
Z0+Rs =2· 50 50+50 =1
The reflection and transmission coefficients looking from line 1 into the junc- tion is
2= (Z0/2)−Z0
(Z0/2)+Z0 = 25−50 25+50 = −1
3 T2=1+2= 2
3
Consequently, the initial voltage launched into both legs (lines 2 and 3) is va=T2vi= 2
3
This voltage (va) travels down each leg and doubles when it arrives at the open circuit (4=5=1). Therefore, the voltage at receiver 1 (vα) occurs att =375 ps, which is the delay of line 1 plus line 2 (the short leg).
vb=va4= 23 vα=va+vb= 43
The voltage at receiver 2 (vA) occurs att =500 ps, which is the delay of line 1 plus line 2 (the long leg):
vA=va+vg=va+va5= 43
For both legs, a reflection of vb=vg= 23 is reflected from the open circuit at the receivers; however, they will arrive at the junction at different times. As seen by the lattice diagram, att =500 ps, vb will arrive at the junction. Part of vb will be reflected back toward receiver 1,
3= (Z0/2)−Z0
(Z0/2)+Z0 = 25−50 25+50 = −1
3 vc=vb3= 2
3
−1 3
= −2 9
and part will be transmitted onto line 1 toward the source and onto line 3 toward receiver 2:
T3=1+3= 2 3
The voltage at receiver 1 att =625 ps (vβ) is calculated:
vd=4vc= −2 9 vβ=vα+vc+vd= 4
3−2 9−2
9 = 8 9
To calculate the voltage at receiver 1 att =875 ps (vψ), it is necessary to account for the portion of the signal reflected from receiver 2 at 500 ps and transmitted into the junction at 750 ps that travels toward receiver 1. This combination of reflections can be seen by observing the lattice diagram, where reflectiongarrives at the junction simultaneously with reflectiond.
ve=3vd= −2 9
−1 3
= 2 27 vf =4ve= 2
27 vg= 2
3 (from above)
vψ =vβ+ve+vf +vgT3+vgT34
= 8 9+ 2
27+ 2 27+2
3 2
3
+2 3
2 3
(1)= 52 27
By observing the lattice diagram, we see that the voltage at receiver 2 att =750 ps is calculated by accounting for the voltage reflected from receiver 1 att =375 ps and transmitted into the junction att =500 ps:
vB=vA+T3vb+T3vb5= 4 3+2
3 2
3
+2 3
2 3
(1)= 20 9
This process can be continued until the waveform has reached steady state. The complete waveforms for this example are shown in Figure 3-36, with the first few reflections (just calculated) labeled. Note that the complicated interactions between the reflections from each leg severely degrade the integrity of the signal.
As more legs are added to the topology, it becomes more sensitive to differences in the electrical length of the legs. Furthermore, a mismatch between the source resistance and the characteristic impedance of line, differences between receiver loads, and impedance deltas between each leg will cause similar instabilities.
−0.5 0 0.5 1 1.5 2 2.5
4.5 4 3.5 3 2.5 2 1.5 1 0.5
0 5
Time, ns
Time, ns
Volts
−0.5 0 0.5 1 1.5 2 2.5
4.5 4 3.5 3 2.5 2 1.5 1 0.5
0 5
Volts
3 4
9 8
9 20
3 4
27 52 vs
0-2 V Rs = Z0
z0 l1
Receiver 2
Receiver 2 Receiver 1 Receiver 1 l2
z0
z0 l2 >l3
Figure 3-36 Signal integrity of a T-topology when the leg lengths are not equal.
So what can we learn form this? The answer is:symmetry. Whenever a topol- ogy is considered, the primary area of concern is symmetry. Make certain that the topology looks symmetrical from the point of view of any driving agent. This is usually accomplished by ensuring that the lengths, impedances, and loading are identical for each leg of the topology. The secondary concern is to minimize the impedance discontinuities at the topology junctions, although this may be impossible in some designs.