5.2 The ATLAS Pixel Detector
5.2.1 The Pixel Detector Module
which the bulk changes from n-type to p-type, and the depletion zone grows with increasing bias voltage from the n-side to the p-side. In this case the sensor can be used if it is not fully depleted, because the depletion zone extends from the pixels.
Figure 5.3: The three basic components of a pixel detector module: a flex hybrid containing control circuits (top), a silicon sensor (middle) and the front-end (FE) electronics (bottom). [69]
Each pixel is bump-bonded to one of the sixteen front-end (FE) chips per module. The chip contains 2880 pixel cells arranged in an 18×160 matrix. The components of single cell in the FE chip are shown in Fig. 5.4. Each cell consists of an analogue and a digital block. In the analogue block, the sensor charge is amplified and compared to a programmable threshold. In the digital block, the pixel hit address and timestamp of the leading and trailing edge are transferred to buffers located in the peripheral regions of the chip and stored for 3.2µs. If a trigger signal with the same timestamp is received within that time the hits are read-out, otherwise they are discarded.
Most pixels are 50 x 400µm in size. To ensure sensitivity in the regions between chip boundaries, 11% of the pixels have a size of 50 µm ×600 µm and are referred to as long pixels. A different strategy is used to cover the chip boundary in the short pixel direction, because such an increase in
Select EnHitBus TDAC0-6
FDAC0-2
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To A/D C
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SEU tolerant RAM
Decoupling capacitor Active biasing Global threshold D/A C
Bump-bond pad Charge injection
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Figure 5.4: The components of a pixel FE chip [3]
size would degrade the measurement precision. Instead, multiple pixels are read-out by the same read-out channel. The 8 pixels lying in the boundary region are connected to one of the neighbouring pixels as illustrated in Fig. 5.5. These pixels are referred to asganged pixels. The connections are only made to every second pixel to allow ambiguities to be resolved in the clustering algorithms.
The pixels between the ganged pixels are referred to asinter-ganged pixels. Combinations of the two categories are possible for pixels, which lie close to the chip corners. In total there are five different types of pixels: normal (93.7%), long (10.6%), ganged (2.2%), inter-ganged (1.6%), long-ganged (0.3%) and long inter-ganged (0.2%). This connection strategy is the reason that the number of read-out channels (46080) differs from the number of pixels (47232) in a module.
The charge sensitive preamplifier contains a feedback circuit in which the constant discharge current saturates at high signal amplitudes. This means that the return to baseline of the pulse is close to linear, such that the width of the discriminator pulse output is proportional to the input charge. The width of the discriminator output, the so-called Time-Over-Threshold (ToT) is therefore used to measure the amplitude of the signal. The ToT is measured by counting in units of the 40 MHz MCC clock. As this frequency is the same as the LHC bunch crossing frequency,
long ganged interganged long ganged long inter-ganged normal
Figure 5.5: The six different classes of pixel. The normal pixels (white) are50×400 µm in size.
The long pixels (blue) are 600 µm long. The ganged pixel (yellow) are two pixels which share a read-out channel. The inter-ganged pixels (dark yellow) are normal pixels between ganged pixels.
The combinations of the two are the long ganged pixels (red) and the long inter-ganged pixels (dark) red. The connections between the ganged pixels are indicated.
the units typically used are called bunch crossings (BC).
Each pixel cell in the FE chip contains a 14-bit control register, which is used to tune several parameters for each pixel. The group of bits used to control a specific parameter is called a Digital- to-Analog-Converter (DAC). The most commonly used are the 3-bit FDAC, which are use to trim the feedback current to tune the ToT response and the 7-bit TDAC, which are used to trim the threshold. In addition, there are global DACs, which are used to tune the scale of the feedback current (IFDAC) and threshold (GDAC) for all pixels on a single FE chip.
Signal and power are routed to the module through a 100 µm thick flexible printed circuit, which is called a flex-hybrid. The module controller chip (MCC) is situated on the flex-hybrid. The barrel modules are connected to the electrical services via microcables on an additional foil called a pigtail. The micro-cables for the end-cap modules are attached without the pigtail connection.
The presence or absence of this pigtail is the only difference between modules in the barrel versus the end-cap.
The MCC controls the modules. During module configuration it writes values to the global FE chip registers and parameters for each pixel cell. The MCC distributes the L1 triggers, and the reset, calibration and timing signals to the FE chips. Finally, the MCC reads out and builds events.
To achieve this, the data received from the FE are deserialised and buffered into First In, First
Out electronic control circuits (FIFOs) by the Receiver. The Event Builder then extracts the data from the FIFOs and builds the event. The completed event is then transmitted upstream to the Read-Out Driver (ROD).