Number of stacks
A.2 Step-by-step Description of the Flow
A.2.3 Place and Route
Once we have the synthesis up and running, the next step is Place and Route. We will use Cadence Encounter to do this. Keep in mind, this is not just a matter of placing the gates and creating interconnections; the tool also takes care of timing while routing, meaning metal-to-metal routing capacitance is taken into account while the tool routes signals. As
a result, depending on the area constraints or the density, it may take several iterations for the tool to converge upon a routing strategy.
To invoke Cadence Encounter:
$ cd myDesign/pnr
$ /software/opt/CDS/cadence2007/edi91/tools.lnx86/bin/encounter
Use File->Import Design and fill up the fields as shown in Figure A.3:
Click the Advanced tab and click Power. Putvdd! in Power Nets and gnd! in Ground Nets. Click RC Extraction. Under Typical Capacitance Table File, point to the captable for the process technology. Click OK. You can also choose to save the configuration for future use by clickingSave. The main Encounter window should now look something like in Figure A.4. Note that the input and output ports are all clustered in the bottom left.
Figure A.3: Importing design to Encounter - 1
We can now specify the floorplan we want including the aspect ratio and other details.
To do this, use Floorplan->Specify Floorplan. Most of the fields are self-explanatory, for
core margins specify how much room is to be left on all sides for power and ground rings.
The values in Figure A.5 usually work well for smaller designs, for bigger designs they will need to be changed. The core margins are also dependent on the number of inputs and outputs the design has.
Figure A.4: Main Encounter window after importing design The final floorplan window will now look like Figure A.5.
Figure A.5: Specifying floorplan details for the design.
Power and ground rings will be added now using Power->Power Planning->Add Ring.
Note that in this example we are using M5 and M4 as power metals. Depending on the size of the design, higher or lower metal levels may be used. Click the Via Generation tab.
At the time of creation of this document, the metal layers are read from a template .lef file.
In IBM 32nm SOI, the higher metal levels are not named as Mx. As a result, for simplicity, we are going to use only metals 1 through 5 for the current design. Select metal5 as the Top stack via layer and metal1 as the bottom stack via layer. The window should now look like Figure A.6.
Figure A.6: Power ring settings in detail.
Press OK. You can see that the power rings have been added around the periphery. Now we need to add power stripes to create some sort of a power grid. This is particularly useful for bigger design. The number of stripes as well as their spacing can be specified. Click Power->Power Planning->Add Stripe and follow sample settings in Figure A.7. Again, click Via generation and select metal5 as the top metal layer and metal1 as the bottom metal layer. After adding the stripes and the ring, the encounter window should look like in
Figure A.7: Adding power stripes to the design.
Figure A.8: Encounter window after adding power ring and stripes.
Now we can specify locations of the I/O pins. To do this go toEdit->Pin Editor. Finish assigning pin locations as shown in Figure A.9. Note that multiple I/O pins can be assigned by selecting them through shift+click. You should see the pins being spaced out along the edge you specified in this step. If there are too many pins along one edge, the tool pops up a
warning if it violates DRC. Now we are ready to place the standard cells. ClickPlace->Place Standard Cell.
Figure A.9: Specifying pin locations and spacing.
Open up a detailed option box using the Mode button. Since we have already placed the pins, uncheck the Place IO Pins box. Make sure Run Timing Driven Placement is checked. Remember, keep checking the terminal window for warnings or errors that may have occurred. After running the placement, click the button shown in Figure A.10.
Figure A.10: All standard cells placed in the design.
We will now hook up the power and ground nodes of the standard cells. For this,Power-
>Connect Global Nets. For the standard cells in our present design, the ground and supply connections are named VDD & VSS. Under Connect, selectPin and enter the standard cell pin name, then enter the corresponding global net name (e.g., vdd and gnd) in To Global Net. Also, we need to specifyTie Hi &Tie Low options under Connect, selecting Tie High (or Tie Low) instead ofPin, making sure that thePin Name(s) field is empty, then entering the corresponding global net name underTo Global Net. These settings are shown in Figure A.11.
Once this step is done, go to Route->Special Route. Again, change theTop Layer option to metal5. And in the Via Generation tab, specify the top stack via layer as metal5 at the two places. Click OK and you should see the supply connections routed for each cell. For bigger designs, we need to design a clock tree at this step, but for simplicity we are skipping this step.
Figure A.11: Adding global net connections.
We are now ready to do a detailed route. Select Route->NanoRoute->Route. Select Mode, change the routing metal layers to metal5 and metal2. Note that in our standard cells, all the pins are on metal2. So we are making sure the tool does not route using metal1.
This is to prevent possible occurrences of DRC errors within the cell, once the tool routes using metal1. You can set multiple options here in the various tabs. These govern how strict the routing will be, how many vias per connections, antenna violations, etc. One important option is under the AdvDRC tab, where you check the Enclose Via Completely in Standard Cell Pin. This prevents a lot of DRC errors due to vias sticking out of small metal islands.
Set the number of cores and start the process by clocking OK. The tool will take several iterations to converge. It will show an X box where it thinks there is a DRC error. The encounter window now should look something like in Figure A.12.
Figure A.12: After nanoroute.
You may want to add filler cells at this point, buy choosing Place->Physical Cell->Add Filler. Select the filler cells and they should be placed in the vacant spaces.
We are now ready to export the GDS to Cadence. File->Save->GDS. Leave the options default except the map file. This is a custom encounter map file not to be confused with the normal gds map file you use with virtuoso. For IBM32nm SOI, the map file is in
/home/kaushikd/Digital_Synthesis/dno/NangateOpenCellLibrary_PDKv1_3_v2010_12/custom- Encounter_ibm.map
or
/home/kaushikd/Digital_Synthesis/dno/NangateOpenCellLibrary_PDKv1_3_v2010_12/custom- Encounter_ibm_mod.map
You also need to export the schematic netlist using the following in the encounter com- mand line:
saveNetlist decoder4.pnr.v -excludeLeafCell
Now we can import the layout and the schematic into virtuoso.