Electronic properties of tunnel oxide layer in silicon nanocrystal memory
3.4 Quantitative analysis and discussion
almost negligible compared with that on SiO2, the etching process was severely hindered when reaching the Si-rich nanocrystal region at the end of the 8s etching period. The sample surface variation thus corresponds to the curved envelope surface of the Si-rich region [Fig. 3.4(b)], which includes Si nanocrystals and perhaps excess Si in SiO2 and amorphous Si as well. In the C-AFM experiments, the electric currents depend primarily on the local thickness of the SiO2 film, while nanocrystals also play an important role by decreasing the effective oxide thicknesses and greatly increasing the current magnitudes [Fig. 3.4(c)].
Figure. 3.5. I-V characteristics (squares: from 0 to +6 V; circles: from 0 to -6 V) corresponding to the spot with highest conductance, the spot with lowest conductance, and the average over all spots in the scanned area.
Figure 3.6. Histogram of current values in the current images at +3.52 V and -4.55 V, respectively. The bias voltages were chosen so that the average current is 0.1 nA for both situations. The equivalent oxide thicknesses (EOTs) are given for current values under positive tip bias.
of conductance for the whole area. An estimation of equivalent oxide thicknesses was made by calculating tunneling current densities through the film and comparing that with the theoretical and experimental curves92,93,94 showing the oxide thickness dependence of electron tunneling currents, with the difference in work function taken into account. The contact area between the AFM tip and sample surface may vary during the scan. An estimated average of 100 nm2 with a range between 30 nm2 and 300 nm2 was based on similar experiments on device grade SiO2 with known thickness. This range is consistent with the resolution of the C-AFM topographic images. In addition, due to the extremely high sensitivity of currents to local variations of oxide thickness, i.e., one order of magnitude change in current density only corresponds to less than 0.3 nm change of local oxide thickness, the contact area need not be known precisely. Under positive tip bias, calculation reveals that the estimated equivalent oxide thicknesses corresponding to the largest, smallest, and average currents are 1 ± 0.15 nm, 2.4 ± 0.15 nm and 1.7 ± 0.15 nm, respectively.
These values are much smaller than the actual thicknesses of the SiO2 layer, which is about 5.1 ± 1.5 nm. Such a big difference suggests the Si nanocrystal doped SiO2 layer has a largely increased conductivity. Most likely, the concentration of implanted silicon is close to or even above the percolation threshold, so the separations between nanocrystals are not well maintained, creating high conductance paths. Recalling the upper limit of nanocrystal density, which is 3 × 1013 cm-2, and assuming no implanted Si was lost into substrate during annealing and that half of the nanocrystals were kept in our sample, there should be 15 nanocrystals with sizes about 2.5 nm within the 10 nm ×10 nm × ( ~5 nm) region of SiO2 film underneath the C-AFM tip. Since a volume of (2.5 nm)3 can barely
hold one nanocrystal, there are totally 4 × 4 × 2 spaces to hold the 15 nanocrystals.
Statistics show that it is certain that some nanocrystals will occupy the “upper-floor”
spaces and some nanocrystals will occupy the “lower-floor” spaces, and nanorystals contact each other to some extent, both laterally and vertically. This can create high- conductance path underneath the AFM tip at any time during scanning.
The depth profile of implanted Si with a peak value of 20% excess Si atoms is very similar to the situation of percolation threshold in the simulation work of Müller et al.95 According to their research, for high concentrations Si separates by spinodal decomposition during annealing. The nanocrystals become larger and may even interconnect, and the interface minimization of nonspherical Si structures leads to a narrowing of the denuded zone, which, for optimal device architectures, should be free of nanocrystals with a thickness of a few nanometers above the Si/SiO2 interface [Fig.
3.7(a)]. Moreover, because larger nanocrystals dissolve more slowly, annealing time may not be enough to completely dissolve nanocrystals in the denuded zone, which would cause the scenario mentioned above. The reduced and contaminated deluded zone and the interconnections between nanocrystals [Fig. 3.7(b)] increased the overall magnitude of tunneling currents through the tunnel oxide.
One major advantages of nanocrystal memory is its immunity to oxide defects. In general, several leaking paths won’t affect the function of the memory device. However, the histogram of current values [Fig. 3.6] shows that the equivalent oxide thicknesses are between 1.5 nm and 2.0 nm for most spots, and are even close to 1 nm for some spots.
The actual distances between the contacted nanocrystals and the channel should be even smaller than these values, considering the cross section of nanocrystals is much smaller
Figure 3.7. Cross section of nanocrystal distribution in the (a) “nucleation and growth”
regime and (b) “spinodal decomposition” regime with limited annealing time.95
than the contact area of the AFM tip. The high conductance observed at most spots in the scanned area is responsible for the relatively short retention time of the memory device, which is about 1 hour to lose the initial 30% of electrons in our capacitance decay measurements. The tunneling of holes cannot be tested in C-AFM because electrons are still the dominant carriers even under negative tip bias, which is different from the situation in device operation. As stated in the Chapter 2, the barrier height for holes is larger than that for electrons, and consequently a much longer retention time for holes was observed.
When studying the I-V curves in Figure 3.5, the max/min ratio under positive tip bias was found to be much larger than that under negative tip bias. The smaller dependence of current on surface morphology under negative tip bias was also noticed in the histograms
of current values [Fig. 3.6]. This difference can be due to the non-ohmic contact between the metallic AFM tip and the Si nanocrystal layer. In fact, this contact can be viewed as a Schottky barrier. It can be neglected in the C-AFM setup under positive tip bias [Fig.
3.8(a)] but has to be taken into consideration when the tunneling current through oxide under negative bias is comparable to the saturation current of the Schottky barrier [Fig.
3.8(b)], which makes it the limiting factor for increasing the tunneling current. However, because the oxide voltage under negative tip bias is bigger than that under positive tip bias with the same magnitude, the tunneling current of the former could exceed that of the latter when the tunneling current is far below the saturation current of the Schottky barrier, i.e. in the area where the oxide is relatively thick. In addition, hole tunneling also makes a contribution to the total current under negative tip bias. For simplicity, most of our analysis and discussion of electron tunneling is focused on the I-V characteristics obtained under positive tip bias.
Figure 3.8. Energy band diagrams for positive tip bias (a) and negative tip bias (b) in the C-AFM. χ(Si)=4.05 V, Φ(PtIr5)=5.3 V, measured barrier height ΦB=0.9 V.