Reliability Comparisons by EPP - Area- vs. Timing-Constrained Implementations

6.2 Area- vs. Timing-Constrained Implementations

6.2.3 Reliability Comparisons by EPP

In order to understand the impact that topology has on error propagation probability, the data were analyzed in two ways: (1) the average error propagation probability indicates the vulnerability of an entire circuit, and (2) the “greater-than-0.5” metric indicates how many individual cells within the design have an EPP greater than 50%. The average EPP is important because it informs mitigation strategies that attempt to harden an entire circuit.

For example, the use of a radiation-hardened cell library would improve the average soft error rate of a circuit. The “greater-than-0.5” metric is important for mitigation strategies that implement selective node hardening. For example, selective transistor sizing for reli-

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FIT Rate

Circuit

Area Timing

Figure 6.3: FIT rate for selected ISCAS85 benchmark circuits (range: 200-7000 cells), separated by area- and timing-constrained implementations.

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FITRate

Circuit (LgSynth91)

Smallest Fastest

103

Figure 6.4: FIT rate for selected LgSynth91 benchmark circuits(range: 90-10000 cells), separated by area- and timing-constrained implementations.

ability improvement requires identification of the highly vulnerable nodes to be hardened (Zhou and Mohanram,2006).

The area- and timing constrained implementations of the ISCAS85 benchmark circuits are compared for error propagation probability in Figures 6.5 and 6.11. The area- and timing constrained implementations of the LgSynth91 benchmark circuits are compared for error propagation probability in Figures 6.6, 6.7, 6.8, 6.9, 6.10, 6.12, 6.13, 6.14, 6.15, and 6.16. In the figures, the LgSynth91 benchmark circuits are arranged by size from most number of cells to least number of cells. The area-constrained implementations have a higher average EPP than the timing-constrained implementations (Figures 6.5, 6.6, 6.7, 6.8, 6.9, and6.10). This result is consistent with the frequency of XOR and XNOR cells previously discussed. However the number of cells of the timing-constrained implementations with EPP greater than 0.5 are consistently greater than the number of cells of the area-constrained implementations with EPP greater than 0.5. This result, shown in Figures 6.11, 6.12, 6.13, 6.14, 6.15, and 6.16 imply that timing-constrained implementations con- tain more high-EPP cells than area-constrained implementations, even when the average EPP is lower. This result is probably due to dueling mechanisms: (1) timing optimizations create shorter worst-case paths which increases the probability of an error reaching the output and (2) timing optimizations create longer best-case paths (i.e., the logic depth metric used in this study) in an attempt to balance the worst-case path, which decreases EPP through increased logical masking. Fig. 6.17 supports this theory as there are more nodes with a logic depth of 1 or 2 for the timing-constrained implementation. Additionally, the timing-constrained implementations have nearly twice the frequency of inverters as the area-constrained implementations. Since inverters along a highly-vulnerable path do not logically mask errors, the higher frequency of inverters in timing-constrained implementations could skew both the average EPP and the number of cells with EPP greater than 0.5.

The higher frequency of inverters also explains why the timing-constrained implementations have longer logic depths than area-constrained implementations, even though the delay for timing-constrained implementations is smaller.

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Average Error Propagation Probability

Circuit

Area Timing

Figure 6.5: Error propagation probability average for the selected ISCAS85 benchmark circuits (range: 200-10000 cells) separated by area-constrained and timing-constrained implementations.

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Average Error Propagation Probability

Circuit

Area Timing

Figure 6.6: Error propagation probability average for the selected LgSynth91 benchmark circuits (range: 8000-700 cells) separated by area-constrained and timing-constrained implementations.

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Average Error Propagation Probability

Circuit

Area Timing

Figure 6.7: Error propagation probability average for the selected LgSynth91 benchmark circuits (range: 80-400 cells) separated by area-constrained and timing-constrained implementations.

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Average Error Propagation Probability

Circuit

Area Timing

Figure 6.8: Error propagation probability average for the selected LgSynth91 benchmark circuits (range: 80-400 cells) separated by area-constrained and timing-constrained implementations.

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Average Error Propagation Probability

Circuit

Area Timing

Figure 6.9: Error propagation probability average for the selected LgSynth91 benchmark circuits (range: 300-1700 cells) separated by area-constrained and timing-constrained implementations.

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Average Error Propagation Probability

Circuit

Area Timing

Figure 6.10: Error propagation probability average for the selected LgSynth91 benchmark circuits (range: 150-2000 cells) separated by area-constrained and timing-constrained implementations.

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