It is possible to extend the bandwidth of the DDS chirped pulses by utilizing the super-Nyquist images, as shown in Fig. 2.5. To explore this feature we generated a 1 GHz chirped pulse using a 2 GHz sample clock, so that the full frequency content of the pulse could be recorded with a 4 GS/s digitizer (Fig. A.1). The first image is visible in the spectrogram of the pulse at approximately -10 dBc.
To test the phase stability we averaged 1000 waveforms and found no significant attenuation of the super-Nyquist content, indicating that it is both phase stable and coherent with respect to the normal pulse. Used as is, this chirped pulse could effectively polarize 1.5 GHz of bandwidth. This could possibly be extended by using an appropriate combination of filters and amplifiers operating in saturation.
We also tested the bandwidth of the 2 GHz chirp with the 4 GHz sample clock using a spectrum analyzer and observed a similar frequency envelope extending to 4 GHz. The usable bandwidth of the chirped pulse in this particular example is likely ∼3 GHz, although further tests with a high sample rate digitizer would be needed to better quantify the bandwidth. Additionally, it may be possible to extend the bandwidth to a full 4 GHz by filtering and mixing the main signal with the first image, followed by amplification.
A.1 Stepped-LO Operation
An alternate use for DDS chips in CP-FT spectroscopy, especially at higher fre- quencies, is for ‘stepped’ LO sources, similar to previous AWG-based stepped-LO spectrometers [9, 66]. To demonstrate this capability, we scanned the frequency of the AD9914 from 200-1800 MHz in nine 10 µs steps of 200 MHz (Fig. A.2).
All spurious signals are observed at -40 dBc or less, sufficient for an LO signal in a CP-FT spectrometer. To fully implement this design, a second DDS would be needed along with a method for the generation of multiple chirped pulses per trigger pulse, or the DDS stepped-LO signal could be used in conjunction with an AFG or AWG that supplies the chirped pulse.
Frequency (MHz)
Time (µs)
Power (dBc) 00.511.522.530
1000
2000 00.511.522.53−101 Time (µs)
Electric Field (Volts)
02004006008001000120014001600180020000
5001000
1500 Frequency (MHz)
Magnitude (Arb. Units)
−60
−40
−20
0 FigureA.1:TheunfilteredoutputoftheAD9914DDSfora1GHzchirpedpulse,usinga2GHzsamplingclockfrequency,after1000 averages.Thefirstimageofthechirpisvisiblebetween1GHzand2GHzatapproximately-10dBc.
Frequency (MHz)
Time (µs)
Power (dBc) 01020304050607080901000
1000
2000 0102030405060708090100−101 Time (µs)
Electric Field (Volts)
02004006008001000120014001600180020000
50100 Frequency (MHz)
Magnitude (Arb. Units)
−60
−40
−20
0 FigureA.2:AdemonstrationofthesegmentedLOcapabilityoftheAD9914.Forthisdemonstrationnine10µsstepsof200MHzwere takentocover200-1800MHz.
A.2 Details of AD9914 Implementation
In order for the AD9914 evaluation board (AD9914/PCBZ) to generate chirped pulses it must be configured in the ‘Digital Ramp Generator’ mode within the AD9914 Evaluation Software [56]. To output a single frequency ramp without sustaining the last frequency of the ramp we set the ‘no dwell high’ pin high. Addi- tionally, the ‘Autoclear digital ramp accumulator’ and ‘Autoclear phase accumulator’
pins are set high, so that the frequency and the phase are reset for each chirped pulse.
The AD9914 is advertised with a usable sample clock frequency of up to 3.5 GHz.
To extend the bandwidth of the board, we overclocked the AD9914 with a sample clock at 4 GHz, allowing chirp generation up to 2 GHz. We also increased the band- width of the board by attenuating the sampling clock input to -16 dBm. The cause of the bandwidth dependence on the sample clock power is currently unknown. For the 1.2 µs, 2 GHz chirp used in this thesis, we set the sweep from 0-2000 MHz with a 10 MHz rising step size and 0.006 µs rising sweep ramp rate in the Evaluation Software. This corresponds to stepping the DDS by 200 6 ns, 10 MHz steps for each chirp. With this configuration, the AD9914 board can be triggered from the Evaluation Software with a mouse click.
To synchronize the DDS triggering with that of the CP-FTMW spectrometer, a trigger-in signal is sent to the DRCTL-BUF (pin 63) on the AD9914 chip [196].
However, on the evaluation board this pin is also routed to the USB control chip (for software triggering), which overrides any other direct triggering. To disable the USB control, we removed the R134 0 Ohm resistor connecting the DRCTL-BUF to the USB control [196]. This allows the direct triggering of the chirp from the P102 DRCTL-BUF triple row header on the evaluation board. To achieve coherent signal averaging up to 2 GHz, the digitizer must be directly triggered from the DDS, since it can slip by up to one clock cycle when triggered. The frequency sweep trigger is obtained from the DROVR (pin 65) signal of the AD9914. On the evaluation board this signal is routed to the DROVR-BUF triple row header.
Finally, we observe a slow phase slip of the chirped pulse after many (>500) triggering events. This can be corrected by calibrating the DAC in the Evaluation Software every few seconds. Since the DAC calibration takes 133 µs for a 4 GHz sample clock [56], this does not significantly reduce the repetition rate of the experiment. In this thesis, we performed the DAC calibration with automated mouse clicking software. Brandon Carroll has also developed Arduino software that will automatically calibrate the DAC and control the chirp parameters.
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