21.2 2-wire Serial Interface Bus Definition
21.7 Transmission Modes
21.7.3 Slave Receiver Mode
In the slave receiver mode, a number of data bytes are received from a master transmitter (see Figure 21-15). All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero.
Figure 21-15. Data Transfer in Slave Receiver Mode
S Successfull reception from a slave receiver
Next transfer started with a repeated start condition
Not acknowledge received after the slave address
Arbitration lost and addressed as slave Arbitration lost in slave address or data byte
From master to slave Any number of data bytes
and their associated acknowledge bits This number (contained in TWSR) corresponds to a defined state of the 2-Wire Serial Bus.
The prescaler bits are zero or masked to zero From slave to master
SLA R
RS SLA R
A A DATA P
A P W
MT MR
DATA
A DATA
$08 $40
$48
$38
$50 $58
$38
$10 A
A or A Other master continues
$68 $78
n A Other master
continues
To corresponding states in slave mode A or A Other master
continues
$B0
Device 1 Slave Receiver
SDA
VCC
SCL
Device 3 ... Device n R1 R2 Device 2
Master Transmitter
To initiate the slave receiver mode, TWAR and TWCR must be initialized as follows:
The upper 7 bits are the address to which the 2-wire serial interface will respond when addressed by a master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address.
TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable the acknowledgement of the device’s own slave address or the general call address. TWSTA and TWSTO must be written to zero.
When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own slave address (or the general call address if enabled) followed by the data direction bit. If the direction bit is “0” (write), the TWI will operate in SR mode, otherwise ST mode is entered. After its own slave address and the write bit have been received, the TWINT flag is set and a valid status code can be read from TWSR. The status code is used to determine the appropriate software action. The appropriate action to be taken for each status code is detailed in Table 21-5. The slave receiver mode may also be entered if arbitration is lost while the TWI is in the master mode (see states 0x68 and 0x78).
If the TWEA bit is reset during a transfer, the TWI will return a “not acknowledge” (“1”) to SDA after the next received data byte. This can be used to indicate that the slave is not able to receive any more bytes. While TWEA is zero, the TWI does not acknowledge its own slave address. However, the 2-wire serial bus is still monitored and address recognition may resume at any time by setting TWEA. This implies that the TWEA bit may be used to temporarily isolate the TWI from the 2-wire serial bus.
In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA bit is set, the interface can still acknowledge its own slave address or the general call address by using the 2-wire serial bus clock as a clock source.
The part will then wake up from sleep and the TWI will hold the SCL clock low during the wake up and until the TWINT flag is cleared (by writing it to one). Further data reception will be carried out as normal, with the AVR® clocks running as normal.
Observe that if the AVR is set up with a long start-up time, the SCL line may be held low for a long time, blocking other data transmissions.
Note that the 2-wire serial interface data register – TWDR does not reflect the last byte present on the bus when waking up from these sleep modes.
TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE
value Device’s own slave address
TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE
value 0 1 0 0 0 1 0 X
Table 21-5. Status Codes for Slave Receiver Mode Status Code
(TWSR) Prescaler Bits are 0
Status of the 2-wire Serial Bus and 2-wire Serial
Interface Hardware
Application Software Response
Next Action Taken by TWI Hardware
To/from TWDR To TWCR
STA STO TWINT TWEA
0x60
Own SLA+W has been received; ACK has been
returned
No TWDR action or No TWDR action
X X
0 0
1 1
0 1
Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned
0x68
Arbitration lost in SLA+R/W as Master; own SLA+W has been received; ACK has
been returned
No TWDR action or No TWDR action
X X
0 0
1 1
0 1
Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned
0x70
General call address has been received; ACK has
been returned
No TWDR action or No TWDR action
X X
0 0
1 1
0 1
Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned
0x78
Arbitration lost in SLA+R/W as Master; General call address has been received;
ACK has been returned
No TWDR action or No TWDR action
X X
0 0
1 1
0 1
Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned
0x80
Previously addressed with own SLA+W; data has been received; ACK has been
Read data byte or Read data byte
X X
0 0
1 1
0 1
Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be
0x88 Previously addressed with own SLA+W; data has been received; NOT ACK has
been returned
Read data byte or Read data byte or
Read data byte or
Read data byte 0 0
1
1 0 0
0
0 1 1
1
1 0 1
0
1
Switched to the not addressed Slave mode; no recognition of own SLA or GCA Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = “1”
Switched to the not addressed Slave mode; no recognition of own SLA or GCA;
a START condition will be transmitted when the bus becomes free
Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = “1”; a START condition will be transmitted when the bus becomes free
0x90 Previously addressed with general call; data has been received; ACK has been
returned
Read data byte or Read data byte
X X
0 0
1 1
0 1
Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned
0x98 Previously addressed with general call; data has been received; NOT ACK has
been returned
Read data byte or Read data byte or
Read data byte or
Read data byte 0 0
1
1 0 0
0
0 1 1
1
1 0 1
0
1
Switched to the not addressed Slave mode; no recognition of own SLA or GCA Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = “1”
Switched to the not addressed Slave mode; no recognition of own SLA or GCA;
a START condition will be transmitted when the bus becomes free
Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = “1”; a START condition will be transmitted when the bus becomes free
0xA0 A STOP condition or repeated START condition has been received while still
addressed as slave
No action 0
0
1
1 0 0
0
0 1 1
1
1 0 1
0
1
Switched to the not addressed Slave mode; no recognition of own SLA or GCA Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = “1”
Switched to the not addressed Slave mode; no recognition of own SLA or GCA;
a START condition will be transmitted when the bus becomes free
Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = “1”; a START condition will be transmitted when the bus becomes free
Table 21-5. Status Codes for Slave Receiver Mode (Continued) Status Code
(TWSR) Prescaler Bits are 0
Status of the 2-wire Serial Bus and 2-wire Serial
Interface Hardware
Application Software Response
Next Action Taken by TWI Hardware
To/from TWDR To TWCR
STA STO TWINT TWEA
Figure 21-16. Formats and States in the Slave Receiver Mode
Reception of the own S slave address and one or more data bytes. All are acknowledged
Last data byte received is not acknowledged
Last data byte received is not acknowledged Arbitration lost as master and addressed as slave
Arbitration lost as master and as slave by general call
From master to slave Any number of data bytes
and their associated acknowledge bits
This number (contained in TWSR) corresponds to a defined state of the 2-Wire Serial Bus.
The prescaler bits are zero or masked to zero From slave to master
SLA W A A DATA P or S
A
DATA
A DATA
$60
$68
$80 $80 $A0
$88 A
P or S A
n
$90 $90 $A0
$98
P or S A
Reception of the general call address and one or more data bytes
A
$70
General Call A DATA P or S
A
DATA
$78
A