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Analysis of Via Capacitance in Arbitrary Multilayer PCBs Miroslav Pajovic, Jinghan Yu, and Dragan Milojkovic
Abstract—The signal layer transitions at regions of multilayer printed circuit boards, where high-speed signal lines switch between two signal layers, may affect the board circuit’s signal integrity and electromagnetic compatibility. This study has been focused on the analysis and extraction of values of parasitic capacitance of various designs of through-hole and micro vias as signal layer-changing devices, which are common in practice. The via capacitance is analyzed conceptually by using lumped circuit models for electrically short vias, numerically by the computational calculations based on the transmission line modeling method, and experimentally by labora- tory measurements using a vector network analyzer and an LCR meter.
Index Terms—Lumped circuit models for vias, signal layer transitions in multilayer printed circuit boards (PCBs), signal line discontinuities, via parasitics.
Manuscript received February 3, 2006; revised December 12, 2006. This work was supported by the EMC Compliance Engineering Group of DSSTG of Cisco Systems, Inc.
The authors are with Cisco Systems, Inc., San Jose, CA 95134 USA (e-mail: [email protected]; [email protected]; [email protected]).
Digital Object Identifier 10.1109/TEMC.2007.902382
I. INTRODUCTION
Signal integrity and electromagnetic interference (EMI) investiga- tions of modern high-speed digital circuits present serious challenges for multilayer printed circuit board (PCB) designs. With ever- increasing clock frequencies, data rates, and integrated circuit densities and decreasing signal rise/fall times, signal integrity of PCB cir- cuits require careful considerations. The signal lines need to be well impedance-matched to their drivers, loads, or to other signal lines in order to have minimal effects from discontinuities. One of the typical line discontinuities in high-density PCBs are signal layer transitions or interlayer connections, made by the vias. Intrinsic to all vias are their parasitic capacitances and inductances that create discontinuities in the signal lines. These discontinuities with presence of the PCB resonance effects may lead to additional signal delay, signal reflections, parasitic electromagnetic propagation, and resonance effects in PCBs that con- sequently lead to signal distortions, crosstalk, and EMI problems as discussed in [1]–[6].
In addition to the via inductance and PCB resonances, the via ca- pacitance may have negative impact on signal integrity of high-speed digital signals in multilayer PCBs, especially when transmission lines have more signal vias, as explained in [1, Ch. 5]. Other useful analyses of via capacitance are given in [7]–[9]. In this paper, we have shown the via capacitance models for various physical via designs, which are common in industry, with variety of via radius, via lengths, via clearance to the board planes, and number of stacks per via length.
Furthermore, we have used the method for the extraction of the via capacitance values that is based on a concept of the lumped circuit models for the signal via.
These via models and via capacitance extraction methods are con- firmed by the transmission line modeling (TLM) and simulation method, and by laboratory measurements using a vector network ana- lyzer (VNA) and LCR meter.
II. PHYSICAL ANDCIRCUITMODELS FORVIAS
For typical multilayer PCB structures with a signal line transition, the equivalent hybrid circuit is shown in Fig. 1(a). Here,Csvtis the total via capacitance that includes the capacitances of the signal via body, via pads, and parts of the signal line located on the signal layers next to the signal via.Lsvtis the inductance of the signal via including the inductances of the signal line parts next to the signal via in the antipad via area. The[Zpcb]represents the distributed network associated to the PCB, which acts as a parallel-plane resonator. The plot of the magnitude of the impedanceZˆ11of the circuit in Fig. 1(a), obtained by the TLM method (a dashed curve) and by the VNA measurements (a solid curve), is shown in Fig. 1(b).
The simulations and laboratory measurements are performed on the test PCB with the dimensionsa×b×H= 50mm×50 mm× 2.7 mm. The signal via is one of the typical industry samples that has the following parameters: the number of signal via pads is 3, the via length isH = 2.7mm, the via body radius isr= 0.15mm, the via pads radius isRp= 0.29mm, and the via antipad radius isRap= 0.42mm.
The relative dielectric constant and the loss tangent of the PCB substrate at 10 GHz are 3.9 and 0.016, respectively.
The physical via model, which is formed by a signal via and a ground via spaced by 25 mm, and the VNA setup for measuring the S21parameters of the open-ended signal via, are shown in Fig. 2. The actual plot of the impedance |Zˆ11|was obtained by measuring the S21parameter, and by converting this parameter to the impedanceZˆ11
using (1) as
Zˆ11≈ Sˆ21
2
50 +jωLp
1−Sˆ21
. (1)
Fig. 1. (a) Hybrid via circuit model. (b) TLM-simulated (dashed curve) and VNA-measured (solid curve) impedance magnitude of the open-ended signal via.
Lpis the inductance of the VNA probes that is assumed to be zero after the VNA calibration. The measurement method of the impedance Zˆ11of parallel plane structures is given in [10].
Propagation and cavity effects inside of the parallel-plane PCB struc- ture produce multiple resonances inside the PCB that are shown in the plot of Fig. 1(b). Starting from∼3 GHz and going to∼9.5 GHz, the resonance peaks belong to the even resonance modes: (2, 0)/(0, 2), (2, 2),. . ., (6, 2)/(2, 6). Analysis of the PCB cavity effects on signal lines performance will be the topic of our future work.
For low frequencies, below the PCB resonances, the PCB exhibits the quasi-static behavior and behaves as a parallel-plane capacitorCp. The typical value of ground via inductance is in the order of nanohenry or less. Consequently, the circuit model in Fig. 1(a) will look as in Fig. 3(a). At low frequencies for common industrial PCBs, where the via inductance and the interplane PCB capacitance dominate the via capacitance (i.e., ωLv <<1/(ωCsvt) and 1/(ωCp)1/(ωCsvt), the equivalent circuit in Fig. 3(a) leads to the total via capacitance Csvt, as shown in Fig. 3(c).
A. Extraction of Via Capacitance
At low frequencies, we can neglect the influence of PCB dielectric losses on the via impedance. Therefore, below 1 GHz in the plot of Fig. 1(b), the impedance of the signal via relates mostly to the total signal via capacitanceCsvt, and the magnitude of this impedance may
Fig. 2. Setup for measuring the via impedanceZ11(the ground pins of the probes P1and P2are shorted together, and are connected to the PCB top ground plane).
Fig. 3. (a)–(c) Evolution of the quasi-static via capacitance model.
be expressed by
|Zˆ|= 1 2πf Csvt
. (2)
We used this equation for extracting the total via capacitance values from the impedance|Z|ˆ below 1 GHz obtained by TLM calculations.
III. PRACTICALVIAMODELS, VIACAPACITANCECOMPUTATIONS,
ANDLABORATORYMEASUREMENTS
To obtain the values of via capacitance from practical via models, an experimental platform was designed specifically for this research work. We made laboratory measurements on the platform by VNA and LCR meter. Also, we have performed the computational calculations of the impedance|Zˆ|by the TLM software, and using (2), we have extracted the signal via capacitance values.
A. Measurement of Via Capacitance
We have obtained measurement of the via capacitance by the VNA, Agilent N5230A PNA, and by the LCR meter, Protek Z9218. The via capacitance is directly read out by the VNA, in Smith-chart-impedance mode at 100 MHz and by the LCR meter at 100 kHz. The measurements are performed at the experimental platform with 17 test vehicles with dimensions 50 mm × 50 mm, and the corresponded measurement results are given in Tables I–IV.
B. Initial Model for Signal Via
For cases of signal lines with a signal layer transition, the different via physical models will be derived from the initial via model shown in
TABLE I
VARIATION OF THENUMBER OFVIAPADS AND THEVIALENGTH
TABLE II
INDUSTRIALVIASAMPLES WITHTHREEPADS FORSTRIPLINELAYERTRANSITIONS
TABLE III
VARIATION OF THERADIUS OF THEVIAANTIPADRap
TABLE IV
VARIATION OF THENUMBER OFREFERENCEPLANESALONG THEVIA
Fig. 4, by varying the number of padsnon the via, radiusesr, Rp, Rap, the via heightH, and the number of reference planesN. The signal via model, which is implemented in the PCB with dimensions 50 mm×50 mm×2.7 mm, is one of the typical industry samples, and has the fol- lowing parameters:r= 0.15mm (6 mils),Rp = 0.29mm (11.5 mils), Rap= 0.42mm (16.5 mils),H= 2.7mm (105 mils),n= 14, and N= 12. The PCB dielectric thicknesses hand h1, are 0.254 mm (∼10 mils) and 0.13 mm (∼5 mils), respectively. The thickness of the reference planes, signal lines, and via pads is 0.0165 mm (0.65 mils or 0.5 ounce). The parts of the signal line next to the signal via are 0.127 mm (∼5 mils) wide and(Rap−Rp) = 0.13mm long.
In our test models, relative dielectric constants and loss tangent of the PCB substrates between reference planes differ through the
Fig. 4. PCB with the 14-pad signal via.
Fig. 5. PCB with the three-pad signal via.
PCB stackup, and the resulting average relative dielectric constant is εavr≈4, and the average loss tangent is≈0.02at 500 MHz. We used material vendor numbers to estimate the average values of relative dielectric constant and loss tangent for PCB models.
C. Effects of Via Physical Parameters on Via Capacitance and Computational and Measurement Results
The effect of the via pad on via’s capacitance was analyzed by reducing the number of pads in the via model, shown in Fig. 4, from a total of 14 to 2 via pads, as shown in Fig. 2. All other via parameters such asr, Rp, Rap, H,andNstayed unchanged. TLM method calculation results and VNA and LCR measurement results of the via capacitance for 14, 4, and 2 pads are shown in Table I.
The effect of via height on via capacitance was analyzed by reduc- ing the height of the through-hole via in Fig. 5, while the other via parameters stayed unchanged. After reducing the height fromH = 2.7 mm (105 mil) toH1= 0.3mm (12 mil), the corresponding micro via is shown in Fig. 6. TLM method calculation results and VNA and LCR measurement results of the micro-via capacitance are presented in Table I.
The effect of via body radiusr, via pads radiusRp, and via antipad radius,Rap, was analyzed on the via model shown in Fig. 5, with several typically industrial via sizes for the three-pad via, by changing the parametersr, Rp, and Rapwhile other model parameters stayed unchanged. The corresponding TLM method calculation results and VNA and LCR measurement results of via capacitance are shown in Table II.
Fig. 6. PCB with the micro signal via.
Fig. 7. Two-layer PCB with the three-pad signal via.
The effect of via antipad radiusRap, on via’s capacitance was ana- lyzed by changing theRapof the 3-pad-via also in Fig. 5, with standard parametersr= 0.15mm (6 mils) andRp= 0.29mm (11.5 mils). The corresponding TLM method calculation results and VNA and LCR measurement results are shown in Table III.
The effect of the density of reference planes, which the via passes in the PCB, on the via capacitance was analyzed by gradually reducing the number of reference planes from 12 to 2 on the three-pad-via model.
After the removal of 10 reference planes, the last via model, with only two reference planes, is shown in Fig. 7. The corresponding TLM method calculation results and VNA and LCR measurement results for via capacitances are shown in Table IV.
D. Analytical Estimation of Via Capacitance
In general, by increasing the number of reference planes along a via, the via structure approaches a coaxial form. Practically, the via structure will reach the coaxial form when the spacing between the adjacent PCB reference planes is small and comparable to the spacing between via and the reference planes, i.e., (Rap−r). For a numerical comparison, the capacitance of the related coaxial structure, calculated approximately by the coax-form (3a) and (3b), are added in Tables I–IV
Ccoax= 2πεrε0
H lnRap
Rp
(3a)
Ccoax= 2πεrε0
H lnRap
r
(3b)
whereεr andε0 are the relative dielectric constant of PCB substrate and the dielectric constant in air, respectively. H, Rap, Rp, and r are the via length, the radius of via antipad, the radius of via pad,
and the radius of via body. The coax-form (3a) is used when the ca- pacitance of via pads dominates the capacitance of via body—the case when via has a maximized number of pads. The coax-form (3b) is used when the capacitance of via body dominates the capacitance of via pads—the case when via has a minimized number of pads.
Also, in the last row of Table I, we added values of via capacitance calculated by [1, Eq. (5.1), Ch. 5]. We may see that for the long via with the maximized number of via pads (14), when the capacitance of via pads dominates the capacitance of via body, then (5.1) in [1] gives solid results from practical engineering standpoints. But, for the long via with the minimized number of via pads (2 to 4), the coax-form equation gives pretty more accurate results than (5.1) in [1]. This is because the capacitance of via body dominates the via pad capacitance for vias with the minimized number of via pads. For short (micro) vias, both the equations give solid results. In this case, we used (3a) because the capacitance of via pads dominates the capacitance of via body.
IV. CONCLUSION
In addition to the via inductance and PCB resonant cavity effects, the signal via parasitic capacitance in high-speed signal lines may cause signal integrity problems at high-speed PCB circuitries. This work analyzed vias and signal layer transitions in arbitrary multilayer PCB structures with emphases on the via capacitance that can not be ignored in high-speed PCB design.
As it was shown in this paper, many physical and electrical parame- ters of the PCB and signal vias have considerable influence on the via parasitic capacitances. The negative effect of via capacitance cannot be neglected, but it can be minimized by controlling relevant via and PCB parameters. We analyzed a variety of via designs and their contribution to the via capacitance. The right approach to minimize the capacitance of the through-hole via is first to reduce the number of via pads (i.e., to eliminate the unused via pads). Minimization of the via capacitance by increasing clearance between the via and PCB reference planes is not always an effective solution due to the requirement that the reference planes should be solid planes for the associated high-speed signal lines, which are passing between the vias. However, the most effective solu- tion to minimize the via capacitance is using micro via constructions (short vias), but this solution is sometimes limited by other factors such as higher PCB production cost.
ACKNOWLEDGMENT
The authors would like to thank J. Fisher, Engineering Manager from Cisco Systems, Inc., San Jose, CA, for supporting successful laboratory measurements; and F. Centola, EMC Application Engineer from Flomerics, Inc., Santa Clara, CA, for great help on the TLM computational modeling and simulations.
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