ARM ® Cortex ® -M4 core with FPU and embedded Flash and SRAM
Adaptive real-time memory accelerator (ART Accelerator™)
It balances the inherent performance advantage of the ARM Cortex-M4 FPU over Flash memory technologies, which normally requires the processor to wait for Flash memory at higher frequencies. Based on the CoreMark benchmark, the performance achieved thanks to the ART accelerator is equivalent to running the program in standby state 0 from Flash memory at a CPU frequency of up to 168 MHz.
Memory protection unit
ART Accelerator™ is a memory accelerator optimized for the STM32 industry standard ARM® Cortex®-M4 with FPU processors. To release the full performance of the 210 DMIPS processor at this frequency, the accelerator implements an instruction prefetch queue and a branch cache, which increases the speed of program execution from 128-bit Flash memory.
Embedded Flash memory
All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. The parameters given in Table 34 and Table 35 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. The parameters given in Table 36 and Table 37 is derived from tests performed under the temperature and VDD supply voltage conditions summarized in Table 14.
Unless otherwise specified, the parameters given in Table 48 are derived from tests performed under the conditions summarized in Table 14. Unless otherwise specified, the parameters given in Table 49 are derived from tests performed at room temperature and power supply conditions VDD voltages summarized in Table 14. Unless otherwise specified, the parameters given in Table 67 are derived from tests performed at the ambient temperature, fPCLK2 frequency, and VDDA supply voltage conditions summarized in Table 14.
The parameters listed in Table 72 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. Removed the following sentence from Section: I2C Interface Characteristics: “Unless otherwise noted, the parameters given in Table 56 are derived from tests performed under the ambient temperature, fPCLK1 frequency and VDD supply voltage conditions summarized in Table 14.”.
CRC (cyclic redundancy check) calculation unit
Embedded SRAM
Multi-AHB bus matrix
DMA controller (DMA)
An external power supervisor must be used to monitor the V12 of the logic power domain. The device can be woken up from stop mode by any of the EXTI line (the EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup / tamper / timestamp events, the USB OTG FS /HS generation or the Ethernet generation). They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-fledged general-purpose timers.
Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternative function. The value of this current consumption can be simply calculated using the pull-up/pull-down resistors values given in Table 48: I/O static characteristics. When peripherals are enabled, the power consumption corresponding to the analog part of the peripheral (such as ADC or DAC) is not included.
Refer to the STM32F4xx reference manual for a description of the GPIOx_SPEEDR GPIO port output speed register. Cparazitic represents the capacitance of the PCB (depends on soldering and the quality of the PCB layout) plus the capacitance of the keyboard (approximately 5 pF).
Flexible static memory controller (FSMC)
Nested vectored interrupt controller (NVIC)
External interrupt/event controller (EXTI)
Clocks and startup
Boot modes
Power supply schemes
Power supply supervisor
This supply voltage can drop to 1.7 V when the device is operating in the temperature range of 0 to 70 °C. VBAT functionality is no longer available and VBAT pin must be connected to VDD. All packages, except LQFP64 and LQFP100, allow the internal reset to be disabled via the PDR_ON signal.
Voltage regulator
The PA0 pin should be used for this purpose and act as a power-on reset in the V12 power domain. As long as PA0 is held low, debug mode cannot be used under power-on reset.
Regulator ON/OFF and internal reset ON/OFF availability
Real-time clock (RTC), backup SRAM and backup registers
Low-power modes
The characteristics in Table 30 are the result of tests performed using an external high-speed clock source, and at ambient temperature and supply voltage conditions as summarized in Table 14. The IIO current drawn by the device should always be the absolute maximum respect value specified in Table 12 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. The IIO current supplied by the device must always respect the absolute maximum rating specified in Table 12 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.
For external triggers, a delay of 1/fPCLK2 must be added to the delay listed in Table 67. Updated number of USB OTG HS and FS in Table 2: STM32F405xx and STM32F407xx: features and number of peripherals. Changed fHSE_ext to 50 MHz and maximum value of tr(HSE)/tf(HSE) in Table 30: High Speed External User Clock Characteristics.
Updated maximum PLLI2S input clock frequency and removed related note in Table 37: PLLI2S Characteristics (Audio PLL). Removed replacement function OTG_HS_INTN in Table 7: STM32F40xxx pin and ball definitions and Table 9: Replacement function mapping.
V BAT operation
Timers and watchdogs
Voltages above the absolute maximum values stated in Table 11: Voltage Characteristics, Table 12: Current Characteristics and Table 13: Thermal Characteristics may lead to voltages. The wake-up times given in Table 29 were measured during a wake-up phase with a 16 MHz HSI RC oscillator. The user must ensure that the level on the NRST pin can fall below the VIL(NRST) max level specified in Table 51.
Added tCOUNTER and tMAX_COUNT in Table 52: Characteristics of TIMx associated with the APB1 domain and Table 53: Characteristics of TIMx associated with the APB2 domain. Replaced JTRST with NJTRST, removed ETH_RMII _TX_CLK and adjusted I2S3ext_SD on PC11 in Table 9: Alternate function assignment. Replaced TIM2_CH1/TIM2_ETR with TIM2_CH1_ETR for PA0 and PA5 pins in Table 9: Alternative function assignment.
Inter-integrated circuit interface (I²C)
Universal synchronous/asynchronous receiver transmitters (USART) . 34
The STM32F40xxx features up to three SPIs in slave and master modes in full-duplex and simplex communication modes. SPI1 can communicate at up to 42 Mbit/s, SPI2 and SPI3 can communicate at up to 21 Mbit/s.
Inter-integrated sound (I2S)
Audio PLL (PLLI2S)
Secure digital input/output interface (SDIO)
An SD/SDIO/MMC host interface is available that supports MultiMediaCard System Specification Version 4.2 in three different data bus modes: 1-bit (default), 4-bit, and 8-bit. The SDIO card specification version 2.0 is also supported with two different data bus modes: 1-bit (default) and 4-bit.
Ethernet MAC interface with dedicated DMA and IEEE 1588 support . 36
Serial wire JTAG debug port (SWJ-DP)
Embedded Trace Macrocell™
Parameter conditions
Minimum and maximum values
Typical values
Typical curves
Loading capacitor
Pin input voltage
Power supply scheme
Current consumption measurement
Absolute maximum ratings
These are stress ratings only and functional operation of the device under these conditions is not implied. All main power pins (VDD, VDDA) and ground pins (VSS, VSSA) must always be connected to the external power supply, within the permitted range.
Operating conditions
General operating conditions
VCAP_1/VCAP_2 external capacitor
Operating conditions at power-up / power-down (regulator ON)
Operating conditions at power-up / power-down (regulator OFF)
Embedded reset and power control block characteristics
Supply current characteristics
Typical power consumption versus temperature, run mode, code with data processing running from Flash (ART accelerator ON) or RAM, and peripherals ON. Typical power consumption versus temperature, operating mode, code with data processing running from Flash (ART accelerator OFF) or RAM, and peripherals ON. Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied.
Typical power consumption in operating mode, code with data processing running from Flash memory, regulator ON (ART accelerator enabled. except prefetch), VDD = 1.8 V(1).
Wakeup time from low-power mode
External clock source characteristics
For CL1 and CL2, it is recommended to use external high-quality ceramic capacitors in the range 5 pF to 25 pF (typ.), designed for high frequency applications and selected to match the crystal or resonator requirements (see Figure 32). The crystal manufacturer usually specifies a load capacitance that is the series combination of CL1 and CL2. This value is measured for a standard crystal resonator and can vary significantly with the crystal manufacturer.
This value is measured for a standard crystal resonator and can vary considerably with the crystal manufacturer.
Internal clock source characteristics
PLL characteristics
PLL spread spectrum clock generation (SSCG) characteristics
It should be noted that good EMC performance is highly dependent on the user application and especially the software. The sample size depends on the number of power pins in the device (3 parts × (n+1) power pins). While a simple application is running on the device, the device is burdened by injecting current into the I/O pins programmed in floating input mode.
Note: Refer to the I2S section of RM0090 reference manual for more details on the sampling frequency (FS).
CAN (controller area network) interface
It is recommended to add a Schottky diode (pin to ground) to analog pins that could potentially inject negative currents. EL = Integral Linearity Error: maximum deviation between an actual transition and the endpoint correlation line. When VREF+ and VREF– are not available, they are internally connected to VDDA and VSSA.
When VREF+ and VREF– are not available, they are internally connected to VDDA and VSSA.
Temperature sensor characteristics
V BAT monitoring characteristics
Embedded reference voltage
DAC electrical characteristics
Maximum frequency for a correct DAC_OUT change when small variation in the input code (from code i to i+1LSB). The rest mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic consumption occurs. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier.
The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register.
FSMC characteristics
Camera interface (DCMI) timing specifications
SD/SDIO MMC card host interface (SDIO) characteristics
RTC characteristics
Updated cases of Regulator ON/internal reset ON, Regulator ON/internal reset OFF, and Regulator OFF/internal reset ON in Section 2.2.16: Voltage regulator. Updated Table 39: Flash Memory Characteristics, Table 40: Flash Memory Programming, and Table 41: Flash Memory Programming with VPP. Fixed incorrect reference manual in section 2.2.28: Ethernet MAC interface with dedicated DMA and IEEE 1588 support.
WLCSP90 package information
LQFP64 package information
LQPF100 package information
LQFP144 package information
UFBGA176+25 package information
LQFP176 package information
Thermal characteristics
USB OTG full speed (FS) interface solutions
Added full speed mode Note 2, updated Figure 94: USB controller configured as host only and used in full speed mode and added Note 2, changed Figure 95: USB controller configured in dual mode and used in full speed mode and note 3 added. Appendix A.2: USB OTG high speed (HS) interface solutions: Removed digits USB OTG HS device-only connection in FS mode and USB.
USB OTG high speed (HS) interface solutions
Ethernet interface solutions
PA9/PB13 connection to VBUS removed in Figure 93: USB controller configured as peripheral only and used in full speed mode and Figure 94: USB controller configured as host only and used in full speed mode. Updated Table 49: Output Voltage Characteristics Updated Table 51: NRST Pin Characteristics Updated Table 55: SPI Dynamic Characteristics Updated Table 56: I2S Dynamic Characteristics Removed Table 59.
