FSMC characteristics - Operating conditions

5.3 Operating conditions

5.3.26 FSMC characteristics

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register.

1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.

Table 75. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings⁽¹⁾⁽²⁾

1. C_L= 30 pF.

2. Guaranteed by characterization.

Symbol Parameter Min Max Unit

t_w(NE) FSMC_NE low time 2T_HCLK–0.5 2 T_HCLK+1 ns

t_{v(NOE_NE)} FSMC_NEx low to FSMC_NOE low 0.5 3 ns

t_w(NOE) FSMC_NOE low time 2T_HCLK–2 2T_HCLK+ 2 ns

t_{h(NE_NOE)} FSMC_NOE high to FSMC_NE high hold time 0 - ns

t_{v(A_NE)} FSMC_NEx low to FSMC_A valid - 4.5 ns

t_{h(A_NOE)} Address hold time after FSMC_NOE high 4 - ns

t_{v(BL_NE)} FSMC_NEx low to FSMC_BL valid - 1.5 ns

t_{h(BL_NOE)} FSMC_BL hold time after FSMC_NOE high 0 - ns

tsu(Data_NE) Data to FSMC_NEx high setup time T_HCLK+4 - ns

tsu(Data_NOE) Data to FSMC_NOEx high setup time T_HCLK+4 - ns

th(Data_NOE) Data hold time after FSMC_NOE high 0 - ns

t_{h(Data_NE)} Data hold time after FSMC_NEx high 0 - ns

t_{v(NADV_NE)} FSMC_NEx low to FSMC_NADV low - 2 ns

t_w(NADV) FSMC_NADV low time - T_HCLK ns

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1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.

Table 76. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings⁽¹⁾⁽²⁾

1. C_L= 30 pF.

2. Guaranteed by characterization.

Symbol Parameter Min Max Unit

t_w(NE) FSMC_NE low time 3T_HCLK 3T_HCLK+ 4 ns

t_{v(NWE_NE)} FSMC_NEx low to FSMC_NWE low T_HCLK–0.5 T_HCLK+0.5 ns

t_w(NWE) FSMC_NWE low time T_HCLK–1 T_HCLK+2 ns

t_{h(NE_NWE)} FSMC_NWE high to FSMC_NE high hold time T_HCLK–1 - ns

t_{v(A_NE)} FSMC_NEx low to FSMC_A valid - 0 ns

t_{h(A_NWE)} Address hold time after FSMC_NWE high T_HCLK– 2 - ns

t_{v(BL_NE)} FSMC_NEx low to FSMC_BL valid - 1.5 ns

t_{h(BL_NWE)} FSMC_BL hold time after FSMC_NWE high T_HCLK– 1 - ns t_{v(Data_NE)} Data to FSMC_NEx low to Data valid - T_HCLK+3 ns th(Data_NWE) Data hold time after FSMC_NWE high T_HCLK–1 - ns

t_{v(NADV_NE)} FSMC_NEx low to FSMC_NADV low - 2 ns

t_w(NADV) FSMC_NADV low time - T_HCLK+0.5 ns

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Table 77. Asynchronous multiplexed PSRAM/NOR read timings⁽¹⁾⁽²⁾

Symbol Parameter Min Max Unit

t_w(NE) FSMC_NE low time 3T_HCLK–1 3T_HCLK+1 ns

t_{v(NOE_NE)} FSMC_NEx low to FSMC_NOE low 2T_HCLK–0.5 2T_HCLK+0.5 ns

t_w(NOE) FSMC_NOE low time T_HCLK–1 T_HCLK+1 ns

t_{h(NE_NOE)} FSMC_NOE high to FSMC_NE high hold time 0 - ns

t_{v(A_NE)} FSMC_NEx low to FSMC_A valid - 3 ns

t_{v(NADV_NE)} FSMC_NEx low to FSMC_NADV low 1 2 ns

t_w(NADV) FSMC_NADV low time T_HCLK– 2 T_HCLK+1 ns

t_{h(AD_NADV)} FSMC_AD(adress) valid hold time after FSMC_NADV high) T_HCLK - ns

t_{h(A_NOE)} Address hold time after FSMC_NOE high T_HCLK–1 - ns

t_{h(BL_NOE)} FSMC_BL time after FSMC_NOE high 0 - ns

t_{v(BL_NE)} FSMC_NEx low to FSMC_BL valid - 2 ns

tsu(Data_NE) Data to FSMC_NEx high setup time T_HCLK+4 - ns

tsu(Data_NOE) Data to FSMC_NOE high setup time T_HCLK+4 - ns

t_{h(Data_NE)} Data hold time after FSMC_NEx high 0 - ns

th(Data_NOE) Data hold time after FSMC_NOE high 0 - ns

1. C_L= 30 pF.

2. Guaranteed by characterization.

Table 78. Asynchronous multiplexed PSRAM/NOR write timings⁽¹⁾⁽²⁾

1. C_L= 30 pF.

Symbol Parameter Min Max Unit

t_w(NE) FSMC_NE low time 4T_HCLK–0.5 4T_HCLK+3 ns

t_{v(NWE_NE)} FSMC_NEx low to FSMC_NWE low T_HCLK–0.5 T_HCLK -0.5 ns

t_w(NWE) FSMC_NWE low tim e 2T_HCLK–0.5 2T_HCLK+3 ns

t_{h(NE_NWE)} FSMC_NWE high to FSMC_NE high hold time T_HCLK - ns

t_{v(A_NE)} FSMC_NEx low to FSMC_A valid - 0 ns

t_{v(NADV_NE)} FSMC_NEx low to FSMC_NADV low 1 2 ns

t_w(NADV) FSMC_NADV low time T_HCLK– 2 T_HCLK+ 1 ns

t_{h(AD_NADV)} FSMC_AD(address) valid hold time after

FSMC_NADV high) T_HCLK–2 - ns

t_{h(A_NWE)} Address hold time after FSMC_NWE high T_HCLK - ns

t_{h(BL_NWE)} FSMC_BL hold time after FSMC_NWE high T_HCLK–2 - ns

t_{v(BL_NE)} FSMC_NEx low to FSMC_BL valid - 1.5 ns

tv(Data_NADV) FSMC_NADV high to Data valid - T_HCLK–0.5 ns

th(Data_NWE) Data hold time after FSMC_NWE high T_HCLK - ns

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• CLKDivision = 1; (0 is not supported, see the STM32F40xxx/41xxx reference manual)

• DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM In all timing tables, the T_HCLK is the HCLK clock period (with maximum FSMC_CLK = 60 MHz).

Figure 58. Synchronous multiplexed NOR/PSRAM read timings

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1. C_L= 30 pF.

2. Guaranteed by characterization.

td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25) 0 - ns

td(CLKL-NOEL) FSMC_CLK low to FSMC_NOE low - 0 ns

td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high 2 - ns

td(CLKL-ADV) FSMC_CLK low to FSMC_AD[15:0] valid - 4.5 ns

td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid 0 - ns

tsu(ADV-CLKH) FSMC_A/D[15:0] valid data before FSMC_CLK high 6 - ns th(CLKH-ADV) FSMC_A/D[15:0] valid data after FSMC_CLK high 0 - ns

tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high 4 - ns

th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high 0 - ns

Table 80. Synchronous multiplexed PSRAM write timings⁽¹⁾⁽²⁾

Symbol Parameter Min Max Unit

t_w(CLK) FSMC_CLK period 2T_HCLK - ns

td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) - 1 ns

td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2) 1 - ns

td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 0 ns

t_d(CLKL-

NADVH) FSMC_CLK low to FSMC_NADV high 0 - ns

t_d(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25) 8 - ns

td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low - 0.5 ns

td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high 0 - ns

td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid 0 - ns

td(CLKL-DATA) FSMC_A/D[15:0] valid data after FSMC_CLK

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Figure 60. Synchronous non-multiplexed NOR/PSRAM read timings

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1. C_L= 30 pF.

2. Guaranteed by characterization.

td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25) 2 - ns

td(CLKL-NOEL) FSMC_CLK low to FSMC_NOE low - 0.5 ns

td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high 1.5 - ns

tsu(DV-CLKH) FSMC_D[15:0] valid data before FSMC_CLK high 6 - ns t_h(CLKH-DV) FSMC_D[15:0] valid data after FSMC_CLK high 3 - ns

tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high 4 - ns

th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high 0 - ns

Table 82. Synchronous non-multiplexed PSRAM write timings⁽¹⁾⁽²⁾

1. C_L= 30 pF.

2. Guaranteed by characterization.

Symbol Parameter Min Max Unit

t_w(CLK) FSMC_CLK period 2T_HCLK - ns

td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) - 1 ns

td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2) 1 - ns

td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 7 ns

td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 6 - ns

t_d(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25) - 0 ns

td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25) 6 - ns

td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low - 1 ns

td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high 2 - ns

td(CLKL-Data) FSMC_D[15:0] valid data after FSMC_CLK low - 3 ns

td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high 3 - ns

tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high 4 - ns

th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high 0 - ns

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• ATT.FSMC_WaitSetupTime = 0x07;

• ATT.FSMC_HoldSetupTime = 0x04;

• ATT.FSMC_HiZSetupTime = 0x00;

• IO.FSMC_SetupTime = 0x04;

• IO.FSMC_WaitSetupTime = 0x07;

• IO.FSMC_HoldSetupTime = 0x04;

• IO.FSMC_HiZSetupTime = 0x00;

• TCLRSetupTime = 0;

• TARSetupTime = 0.

In all timing tables, the T_HCLK is the HCLK clock period.

Figure 62. PC Card/CompactFlash controller waveforms for common memory read access

1. FSMC_NCE4_2 remains high (inactive during 8-bit access.

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Table 83. Switching characteristics for PC Card/CF read and write cycles in attribute/common space⁽¹⁾⁽²⁾

Symbol Parameter Min Max Unit

t_v(NCEx-A) FSMC_Ncex low to FSMC_Ay valid - 0 ns

t_{h(NCEx_AI)} FSMC_NCEx high to FSMC_Ax invalid 4 - ns

td(NREG-NCEx) FSMC_NCEx low to FSMC_NREG valid - 3.5 ns

th(NCEx-NREG) FSMC_NCEx high to FSMC_NREG invalid T_HCLK+4 - ns

td(NCEx-NWE) FSMC_NCEx low to FSMC_NWE low - 5T_HCLK+0.5 ns

td(NCEx-NOE) FSMC_NCEx low to FSMC_NOE low - 5T_HCLK +0.5 ns

t_w(NOE) FSMC_NOE low width 8T_HCLK–1 8T_HCLK+1 ns

td(NOE_NCEx) FSMC_NOE high to FSMC_NCEx high 5T_HCLK+2.5 - ns

tsu (D-NOE) FSMC_D[15:0] valid data before FSMC_NOE high 4.5 - ns

t_h(N0E-D) FSMC_N0E high to FSMC_D[15:0] invalid 3 - ns

t_w(NWE) FSMC_NWE low width 8T_HCLK–0.5 8T_HCLK+ 3 ns

td(NWE_NCEx) FSMC_NWE high to FSMC_NCEx high 5T_HCLK–1 - ns

td(NCEx-NWE) FSMC_NCEx low to FSMC_NWE low - 5T_HCLK+ 1 ns

t_v(NWE-D) FSMC_NWE low to FSMC_D[15:0] valid - 0 ns

t_h (NWE-D) FSMC_NWE high to FSMC_D[15:0] invalid 8T_HCLK –1 - ns t_d (D-NWE) FSMC_D[15:0] valid before FSMC_NWE high 13T_HCLK –1 - ns 1. C_L= 30 pF.

2. Guaranteed by characterization.

NAND controller waveforms and timings

Figure 68 through Figure 71 represent synchronous waveforms, and Table 85 and Table 86 provide the corresponding timings. The results shown in this table are obtained with the following FSMC configuration:

• COM.FSMC_SetupTime = 0x01;

• COM.FSMC_WaitSetupTime = 0x03;

• COM.FSMC_HoldSetupTime = 0x02;

• COM.FSMC_HiZSetupTime = 0x01;

• ATT.FSMC_SetupTime = 0x01;

• ATT.FSMC_WaitSetupTime = 0x03;

• ATT.FSMC_HoldSetupTime = 0x02;

• ATT.FSMC_HiZSetupTime = 0x01;

• Bank = FSMC_Bank_NAND;

• MemoryDataWidth = FSMC_MemoryDataWidth_16b;

• ECC = FSMC_ECC_Enable;

• ECCPageSize = FSMC_ECCPageSize_512Bytes;

• TCLRSetupTime = 0;

• TARSetupTime = 0.

In all timing tables, the T_HCLK is the HCLK clock period.

td(NIORD-NCEx) FSMC_NCEx low to FSMC_NIORD valid - 5T_HCLK+ 2 ns

th(NCEx-NIORD) FSMC_NCEx high to FSMC_NIORD) valid 5T_HCLK– 1.5 - ns

t_w(NIORD) FSMC_NIORD low width 8T_HCLK–0.5 - ns

tsu(D-NIORD) FSMC_D[15:0] valid before FSMC_NIORD high 9 - ns

td(NIORD-D) FSMC_D[15:0] valid after FSMC_NIORD high 0 - ns

1. C_L= 30 pF.

2. Guaranteed by characterization.

Figure 69. NAND controller waveforms for write access

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Table 85. Switching characteristics for NAND Flash read cycles⁽¹⁾

1. C_L= 30 pF.

Symbol Parameter Min Max Unit

t_w(N0E) FSMC_NOE low width 4T_HCLK–

0.5 4T_HCLK+ 3 ns t_su(D-NOE) FSMC_D[15-0] valid data before FSMC_NOE high 10 - ns

t_h(NOE-D) FSMC_D[15-0] valid data after FSMC_NOE high 0 - ns

t_d(ALE-NOE) FSMC_ALE valid before FSMC_NOE low - 3T_HCLK ns

t_h(NOE-ALE) FSMC_NWE high to FSMC_ALE invalid 3T_HCLK– 2 - ns

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