I want to thank you all for the friendship and wonderful moments at school to the student members of the Radiation Effects and Reliability group. To comprehensively comment on the design parameters of different sequential logic circuits, a FOM is defined as the inverse of the product of power and SE cross section (PCSP-1).
Contribution
Summary of Document
The representative value of the sensitive area is estimated based on the cross section of a conventional DFF design. A FOM is defined as the inverse of the product of the power and the cross section SE (PCSP-1).
BACKGROUND
Overview of Single-Event Effects in ICs
- SEUs in Logic
- SEUs in FFs
- Radiation Environments Overview
- The Van Allen Belts
- Galactic Cosmic Rays (GCRs)
- Terrestrial Environment
When the electron-hole pairs are generated in or near a p-n junction, the charge is collected in the depletion region of the p-n junction, creating a measurable transient photocurrent [10]. Some protons undergo a nuclear spallation reaction with nuclei (mainly oxygen and nitrogen nuclei) in the atmosphere to produce a number of light particles, including neutrons, photons, electrons, muons, pions, protons and neutrons, when the energetic protons enter the atmosphere ( troposphere and stratosphere) of the Earth.
Previous Approaches to Sequential Logic SEU Analysis
However, at solar maximum when the high-speed solar wind velocities toward Earth act as a shield, GCRs are prohibited from entering a trajectory toward the magnetosphere. Therefore, the irradiance of GCRs peaks at solar minimum and reaches a minimum at solar maximum.
Sources of Power Consumption
- Switching Power of the Circuits
- Short-Circuit Component of Power
- Leakage Component of Power
- Diode Leakage
- Sub-Threshold Leakage
Let β be the size of the transistors and is the duration of the input signal. The duration of the short-circuit current depends on the transition period of the input signal and the output load capacitance [36].
Low-Power Design Methodologies
- Device-driven voltage scaling
- Energy-delay minimum based voltage scaling
- Voltage Scaling Through Optimal Transistor Sizing
- Voltage Scaling Using Threshold Reduction
- Leakage Power Reduction Approaches
Supply voltage can also be scaled down (thus lower switching power) without loss in speed by reducing the threshold voltage of the device. The first reason is that the subthreshold leakage current of the device increases exponentially as the threshold voltage decreases.
Summary
AN EMPIRICAL MODEL FOR PREDICTING THE SE CROSS SECTION FOR COMBINATION LOGIC CIRCUITS IN ADVANCED TECHNOLOGIES. A simplified expression for logic SEU diameter as a function of masking factors is given as [88].
CHARACTERIZATION OF LOGIC SEES FOR ADVANCED TECHNOLOGY
Introduction
In the GHz range of operating frequencies, the contribution of the logical SER to the overall SER is significant [57]. Conventional SER models for logic errors along with experimental SET data are used to explain the combined effects of particle LET, supply voltage, and frequency on logic SER.
Test Circuit Description & Experiments
- Circuit Description
- Test Details
- Experimentally Measuring Logic Cross-Section
To determine the FF cross section alone, shift register chains with only FF (without logic circuits) were used (CREST circuit). The FF, logic and SET cross-sectional error bars were calculated as the standard error of the measurements (StdErr) [67].
Experimental Results
For low LET particles, the slope of the logic cross-section as a function of frequency is not significantly affected by a change in the supply voltage. However, there is a strong dependence on the supply voltage for logic cross sections for high LET particles.
Discussion
The impact of supply voltage and frequency on the other logic circuits (LC-2 and LC-3) diameters at different values of particle LET showed a similar trend to LC-1 (as shown in Fig. III.3). The slope of the curves (as shown in Fig. III.4) indicates the rate of change of Aper gate, TSET + TSH and Aper gate * (TSET + TSH) with supply voltage.
Conclusions
Bhuva, “An empirical model for predicting SE cross-section for combinational logic circuits in high-end technologies.” Based on the SE cross-section of a conventional DFF and the number of sensitive transistors in the DFF, the equivalent sensitive area of a transistor (Aper transistor) can be easily estimated. In this work, the average number of N transistors for different input conditions of logic circuits has been used to estimate the SE cross-section of logic circuits.
Jiang, et al., “An Empirical Model for Predicting SE Cross Sections of Combinational Logic Circuits in Advanced Technologies,” IEEE Trans.
AN EMPIRICAL MODEL FOR PREDICTING SE CROSS-SECTION FOR
Introduction
However, accurate and efficient estimation of the logical SEU cross section has been very difficult, mainly due to the large number of variables involved in the logical SER characterization. This chapter presents an empirical method for estimating the SEU cross-section of combinational logic. Section 4.2 classifies and summarizes different simulation-based and experiment-based approaches for the prediction of the SEU cross-section of combinational logic.
In Section 4.5, the calculated SE combinational logic section and the experimental results are analyzed and compared together with the implications of the proposed methodology.
Background
Proposed method uses experimentally measured cross-section of a conventional D Flip-Flop (DFF) and any arbitrary logic circuit cross-section to obtain necessary parameters. Once a given manufacturing process is characterized in this way, SEU cross section can be predicted for any logic circuit designed/manufactured in that process. The estimated logic SE cross section results obtained with the proposed method are within 2X average error compared to the experimentally measured logic SE cross section.
The availability of such a model will allow designers to evaluate logic SEU cross-section and identify the most sensitive sub-circuits for mitigation to meet IC-level SER specifications during the design phase.
Proposed Empirical Approach
Here Ntransistor is the number of transistors sensitive to the logic block for a SET pulse under given input conditions. The most challenging part of solving (IV.3) is calculating the sensitive area per transistor for a given SET pulse width. This empirical approach assumes a single-value SET pulse width for the entire distribution and uses it to calculate the SE cross section.
Empirical approach proposed here uses a similar technique to estimate the representative values of sensitive area and SET pulse width.
Test IC Designs and Experimental Details
- Circuit Description
- Test Details
- Experimentally Measuring Logic Cross-Section
The estimated SE cross-section agrees well with the experimentally measured SE cross-section for all these logic circuits. The transparent phase of the FF acts as a logic circuit in high-frequency operations, resulting in an increase in the SEU cross-section for FF designs [68]. Depending on the duration of the first phase for SAFF operation, SAFF may exhibit a higher (or lower) SEU cross-section than a conventional DFF design.
The values of the SE cross section estimated using the proposed method were compared with the experimentally measured SE cross section for a variety of logic circuits.
Conclusions
CHARACTERIZATION OF FFS SEES FOR ADVANCED TECHNOLOGY
Introduction
SE mitigation for FF cells is still a major area of research, with many techniques for strengthening FF cells proposed. Conventional FF cells are power and area efficient for nominal operation of less than 1 GHz, but lose power efficiency when operated at 10 GHz. As a result, differential FF designs are fast becoming the design of choice for all communication networks.
Therefore, investigation of SEU characterization and curing techniques for differential FF designs is much needed by the semiconductor design community.
SE Analysis of Conventional DFF and three RHBD FF Designs
- Schematic of FF Designs
- Simulation Results
- Test Details
- Irradiation Test Results
The power, clk to q delay, total number of transistors and IC area of hardened FF and unhardened FF are shown in Table V.I. The DICE-based FF power penalty has the highest value among all other RHBDs when the circuits operate at the same supply voltage. The output of the master stage only has a clock converter delay relative to the output of the slave stage.
Higher value of the slope indicates a greater number of transistors capable of generating SET pulses.
SE Analysis of Sense-Amplifier Based FF Design
- Introduction
- SE Vulnerability of SAFF Design
- First Phase: Data Sampling Phase
- Second Phase: SRAM-Cell Like Phase & Third Phase: SR Latch Hold
- Three Separate Phases of SAFF Comparison
- SEU Response of the SAFF as A Function of Temperature
- Test IC Design and Experimental Details
- Experimental Results & Analyses
- Heavy-Ion Experimental Results
- Alpha Particle Experimental Results
- Conclusions
Effects of temperature, operating frequency and particle LET on SEU cross section for SAFF are evaluated for the first time. In section 5.3.4, the experimental results of temperature, operating frequency and particle LET on SEU cross section for SAFF are provided and analyzed. The critical charge for the slave stage (under third phase) is independent of the differential input voltage.
Critical charge for all three operating levels for SAFF as a function of differential input voltage at nodes In1 and In2.
Summary
If the operating frequency trend were to continue, the SAFF design will exhibit a higher SEU cross-section than DFF designs at 1.6 GHz and higher. The experimental results presented in this work show SAFF SEU cross sections as a function of temperature, operating frequency, and particle LET. This is the first time differential FF has been analyzed for single-event performance on the 16-nm bulk FinFET technology node.
This chapter explains a design methodology that uses empirical models for identifying the optimal combination of topology, supply voltage, and frequency for a given SEU cross-section specification.
Introduction
Designers must identify the best performing (the lowest power requirement) FF designs and logic circuits to meet SER specifications. In this article, various DFF designs and logic circuits are evaluated for given SER specifications to identify optimal supply voltage and speed parameters. Logic circuits fabricated on the 16-nm bulk FinFET CMOS technology node are used to evaluate the effectiveness of the proposed method.
The rest of this section is organized as follows: Section 6.2 presents the proposed analytical method for designing power optimization FFs and logic circuits considering area, speed, and SER specifications.
Design Methodology and Empirical Models
(VI.2) where SER@f is the SER at a certain frequency, V@f is the supply voltage to ensure the operating frequency, γ@f and δ@ f are the adjustment parameters based on data acquisition. @• = 𝜂@•∙ 𝑉@•¢ (VI.4) where P@f is the power consumption of circuits at a certain frequency, η@f is the adaptation parameters based on the Data Acquisition step. The results from the data acquisition step are used to calculate all the fitting parameters in (VI.1)–(VI.4).
Increasing the accuracy/resolution in the data acquisition step can improve the accuracy of the fitting parameters in the qualitative modeling step.
Experimental Details and Results
- Circuit Description and Test Results
- Proposed Model for FF Designs
- Quantitative Modeling Results
- Discussion
- Proposed Model for Logic Circuits
- Quantitative Modeling and Assessment Step
- Discussion
Voltage and frequency test/simulation ranges can be derived from the circuit design Table VI.I Fit parameters (α@V, β@V, γ@f, δ@f and η@f) for DFF design with SVT. By using the proposed model before the traditional logic synthesis step, it is possible to obtain a ranking of FF designs for optimized design specifications. Both the power and cross-section of SE strongly depend on the supply voltage, frequency, node parameters Table VI.VI (γ@f, δ@f and η@f) for three logic circuits.
Symbolic, mathematical and probabilistic models have been Table VI.VII Average number of Ntransistors for various logic gates.
Conclusions
Mahatme, et al., "Comparison of Combinational and Sequential Error Rates for a Deep Submicron Process," IEEE Trans. Mahatme, et al., "Impact of technology scale on the combinational logic soft error rate," IEEE Int. Dabiri, et al., "General Methodology for Soft Fault Aware Power Optimization Using Gate Sizing," IEEE Trans.
Heijmen, et al., “A comprehensive study on the soft error rate of flip-flops from 90-nm production libraries,” IEEE Trans.
Conclusions
Comparison of estimated and experimental value of four different logic circuit
Comparison of estimated and experimental value of two different logic circuit with
SE cross-section as a function of frequency for measured D latch SEUs and estimated
Sensitivity of A per transistor and t pw on predicting SE cross-section of logic circuit LC-1
A conventional D-latch design
Schmitt-trigger-based latch design
Guard-gate-based latch design
4. (a) Schematic design of the DICE-latch containing four storage nodes. (b) The master-
Irradiation data plot of the SEU cross-section as a function of the supply voltage for
Irradiation data plot of SEU the cross-section as a function of frequency for
Irradiation data plot of the cross-section as a function of frequency for conventional
Irradiation data plot of SER as a function of supply voltage for all four DFF designs at
