I would like to express my sincere gratitude to all the professors, post graduate students and lab staff etc. He provides the best support for my experimental research and gives many and meaningful suggestions for my work. Finally, I would like to thank my parents Chunfen Li and Hongbin Xu for their love and support during these two years.
It would have been impossible for me to go through the project without their help and consideration. Black arrows indicate the direction of change in VDD after the high current state is observed. Red arrow indicates the direction of VDD after the high current condition is removed..23 Fig.
The substrate current, including shock ionization current, capacitive coupling, etc., starts to increase with increasing frequency when the operating frequency reaches ~100 MHz ..26.
Background
These types of high current conditions must be addressed and mitigated before they affect the operational behavior of the IC. In addition to the influence of radiation effects, the high current condition can also be caused by changing the operational settings of the circuits. Changing the operating frequency in circuits can also cause the high current condition.
This kind of high current can lead to thermal overflow, which can damage the IC. This thesis shows how a change in operating frequency can lead to a high current condition (similar to sustain) that can be responsible for thermal runaway. Latch-up, especially the single-event latch-up caused by the radiation exposure, is one of the factors that will lead to the high current condition.
The test results of both the single-event latch-up tests and the high-current condition tests triggered by operating frequency changes are discussed in this chapter. The temperature effects of high current mode triggered by latch-up and change of operating frequency are also discussed in the thesis.
![Fig. 1-1 Cosmic rays hit the top of the atmosphere and disintegrate into neutrons, pions, muons, etc [3]](https://thumb-ap.123doks.com/thumbv2/123dok/10732368.0/8.918.127.777.112.563/fig-cosmic-rays-atmosphere-disintegrate-neutrons-pions-muons.webp)
Introduction of the Latch-up
1-4 [16], the base junction of the npn BJT transistor is connected to the collector junction of the pnp transistor. The p-substrate region functions both as the base region of the parasitic npn transistor and as the collector region of the parasitic pnp transistor. Similarly, the base junction of the pnp BJT transistor is connected to the collector junction of the npn transistor.
The N-well region serves as both the base region of the parasitic pnp transistor and the collector region of the npn transistor. If a transient current is generated in the circuits and then one of the transistors turns on. The base/emitter connection of one of the BJT transistors is forward biased, so the base current will be amplified.
The common emitter current gains, βpnp and βnpn, are among the most important factors of the lock-up. 1-3 The cross-sectional view of the latch path in the bulk FinFET technology ([na.
![Fig. 1-2 Parasitic transistors and resistors in the CMOS [15]](https://thumb-ap.123doks.com/thumbv2/123dok/10732368.0/11.918.136.785.609.983/fig-1-2-parasitic-transistors-resistors-cmos-15.webp)
High-Current State Triggered by Frequency-Change
If the supply voltage is lower than the holding voltage, the latch-up could not be maintained [16]. As it has been shown in the previous sections, high current mode of the circuits triggered by latch-up and operating frequency change are included in this thesis. Single-Event latch-up (SEL) event and operating frequency-triggered high-current mode have been characterized in these experiments.
Lach-up events were not observed when the supply voltage was lower than 1.1 V for total fluence greater than ~1×1010 neutron/cm2. For the room temperature tests, single-event latch-up was observed when the supply voltage was increased to 1.4 V. 3-3 shows a typical curve of the I-V characteristics of the latch-up condition after being triggered by the alpha source.
When the supply voltage is ~1.14 V, the current drops back to the initial value, where latch-up does not exist. In this case ~1.14 V could be seen as the 'holding voltage' for the unlock state. When the supply voltage was increased beyond 1.15 V, the latch-up-like failure mechanism was observed.
The supply voltage was gradually increased (keeping the temperature and frequency settings unchanged) to test the critical voltage point when the high current condition occurred. In the initial range (1.12 V ~ 1.2 V) of the supply voltage, the current gradually decreases as the supply voltage decreases. The current will return to the raised value if the supply voltage is raised again (similar to what is observed for shutdown events).
After removing the high current condition, the current was measured with increasing supply voltage (while keeping operating frequency at 2.5 MHz), as shown in the red curve of Fig. Temperature is also expected to affect this latch -up like a high-current condition. Initial observation indicates that frequency-induced high-current event is similar to a latch-up event.
Experimental Details
Information of Test Chips
Setup of the Latch-up Tests
The operating temperature was slowly controlled so that the temperature of the IC does not fluctuate significantly. To monitor the supply current and plot the curve of supply current versus time, the LabVIEW program was used to communicate with the DC power supply and control the supply voltage and monitor the supply current.
Setup of the Tests of Frequency Change-Triggered High-Current State
3-2 shows the SEL FIT rate (or cross section, C.S.) for alpha and neutron tests at different supply voltages for room temperature and elevated temperatures. After the supply current reaches the current limit value, the radiation source is removed and the supply voltage is lowered and the current is monitored in this process. When the supply voltage was reduced, the supply current first decreased linearly and then several step decreases occurred, which could be related to the removal of the micro-closure at many locations.
After the high current condition was reached, the supply voltage was gradually reduced to determine if there is a holding voltage (similar to that seen for shutdown events) beyond which the supply current value returns to normal values for operation of the the district. The current will start to drop sharply if the supply voltage drops close to the holding voltage. However, this does not mean that the SEL event will not occur at lower supply voltage.
It is clear that the increasing temperature will lead to a reduced value of the threshold triggering supply voltage. Sudden increases in supply current are observed in both latch-up event and frequency-induced high-current event. 34;Alpha-particle soft-error rates for D-FF designs in 16-Nm and 7-Nm Bulk FinFET technologies." In 2019 IEEE International Reliability Physics Symposium (IRPS), p.
34; Scaling of CMOS IC technology and its impact on burn-in. "IEEE Transactions on Device and Materials Reliability 4, no. 34; Dynamic Thermal Management for High-Performance Microprocessors." In Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture, pp. 34; A self-consistent junction temperature estimation methodology for nanometer-scale ICs with implications for performance and thermal management. “In IEEE International Electron Devices Meeting 2003, pp.
34; Single-event hatch-up hardening using TCAD simulations in 130nm and 65nm embedded SRAM in flash-based FPGAs. "IEEE Transactions on Nuclear Science 62, no. 34; Single-event hatchup modeling based on coupled physical and electrical transient simulations in CMOS technology." IEEE Transactions on Nuclear Science 61, no. 34; Single-event hatchup modeling based on coupled physical and electrical transient simulations in CMOS technology." IEEE Transactions on Nuclear Science.
34;Autonomous bit error rate testing at multi-gbit/s rates implemented in a 5AM SiGe circuit for radiation effects self-test (CREST)." IEEE Transactions on Nuclear Science 52, no. 34;Numerical simulation of single-event latching in the temperature range of 77-450 K." IEEE Transactions on Nuclear Science 42, no. 34; Modeling Elevated Temperature Impact on Single-Event Transients in Advanced CMOS Logic Beyond the 65-nm Technology Node." IEEE Transactions on Nuclear Science 61, no.
Experimental Results
Experimental Results of the SEL Tests
Experiment Results of the Tests of Frequency Change-Triggered High-Current State
The first test consisted of changing the operating frequency from a low value (2.5 MHz) to a high value (above 500 MHz), while keeping the supply voltage below 1.15 V. If the high current was not observed after the process for these experiments (changing frequencies as shown in Table 2.1) was repeated 20 times, it was assumed that the high current condition will never occur under that particular condition. This behavior was observed for all supply voltage values above 1.15 V and all frequency values above ~834 MHz (actual frequency measured at this supply voltage) at room temperature.
It is clear that the current value will not return to the increased value related to the high current state, indicating that this high current state disappears during the holding voltage. The purpose of the work illustrated in this thesis was to provide an initial analysis for the behavior and mechanisms of the phenomena in the high-current state triggered in ICs fabricated at the 7-nm node. The performance of the high current mode, either through SEL event or operating frequency change, has been introduced in previous chapters.
When the supply voltage is lower than 1.4V, the question remains whether the SEL event will occur anyway, as the time to trigger the event increases significantly at lower supply voltages. If a particular supply voltage value is defined as a critical value at which an SEL event will "never occur", then the associated supply voltage is treated as the SEL event threshold value. It is hypothesized that all of these factors together may be sufficient to mediate the biasing of the base-emitter junction of the parasitic bipolar transistor to trigger a latch that may be responsible for triggering the frequency-induced high-current state.
High-current states triggered in the circuits, including single-event latch-up state and operating frequency-triggered high-current state, have been discussed in this thesis. Both types of high current modes are closely related, providing valuable information in the field of reliability of the digital circuits for researchers and engineers.
Analysis and Conclusions
![Fig. 1-4 The equivalent circuits of a typical latch-up structure [16]](https://thumb-ap.123doks.com/thumbv2/123dok/10732368.0/13.918.332.585.149.476/fig-1-equivalent-circuits-typical-latch-structure-16.webp)
