List of tables
TXE/RXNE/BSY behavior in Master/full-duplex mode (BIDIMODE=0 and . RXONLY=0) in case of continuous transfers. TXE/RXNE/BSY behavior in Slave/full-duplex mode (BIDIMODE=0, . RXONLY=0) in the case of continuous transfers.
1 Documentation conventions
List of abbreviations for registers
Glossary
Peripheral availability
2 Memory and bus architecture
- System architecture
- I-bus
- D-bus
- S-bus
- DMA memory bus
- DMA peripheral bus
- Ethernet DMA bus
- USB OTG HS DMA bus
- LCD-TFT controller DMA bus
- DMA2D bus
- BusMatrix
- AHB/APB bridges (APB)
- Memory organization
- Memory map
- Embedded SRAM
- Flash memory overview
- Bit banding
- Boot configuration
This bus connects the instruction bus of the Cortex®-M4 with the FPU core of the BusMatrix. The targets of this bus are data memories: internal SRAMs (SRAM1, SRAM2, SRAM3), internal Flash memory and external memories through FSMC/FMC.
3 Embedded Flash memory interface
Introduction
Main features
Embedded Flash memory in
STM32F405xx/07xx and STM32F415xx/17xx
Embedded Flash memory in STM32F42xxx and STM32F43xxxSTM32F43xxx
Optional bytes to configure read and write protection, BOR level, watchdog, dual bank boot mode, dual bank feature, software/hardware, and reset when the device is in standby or shutdown. The dual bank feature on 1 Mbyte devices is enabled by setting the DB1M option bit. To obtain dual-bank flash memory, the last 512 Kbytes of one bank (sectors [8:11]) are restructured in the same way as the first 512 Kbytes.
The sector numbering of double-bank memory organization differs from the single-bank memory: the single-bank memory contains 12 sectors while the double-bank memory contains 16 sectors (see Table 7: 1 Mbytes flash memory single-bank vs double-bank organization (STM32F42xxx and STM32F43xxx) ). Refer to Table 8: 1 Mbyte Single Bank Flash Memory Organization (STM32F42xxx and STM32F43xxx) and Table 9: 1 Mbyte Dual Bank Flash Memory Organization (STM32F42xxx and STM32F43xxx) for details on 1 Mbyte Single Bank and 1 Mbyte Dual Bank.
Read interface
- Relation between CPU clock frequency and Flash memory read time
- Adaptive real-time memory accelerator (ART Accelerator™)
After reset, the CPU clock frequency is 16 MHz and 0 wait state (WS) is set in the FLASH_ACR register. Program the new number of wait states to the LATENCY bit in the FLASH_ACR register. Check that the new number of wait conditions are taken into account to access the Flash memory by reading the FLASH_ACR register.
Check that the new number of wait states are used to access Flash memory by This function can be activated by setting the instruction cache enable (ICEN) bit in the FLASH_ACR register.
Erase and program operations
- Unlocking the Flash control register
- Program/erase parallelism
- Erase
- Programming
- Read-while-write (RWW)
- Interrupts
Check that no Flash memory operations are in progress by checking the BSY bit in the FLASH_SR register. Set both MER and MER1 bits in the FLASH_CR register (on STM32F42xxx and STM32F43xxx devices). Check that no main Flash memory operation is in progress by checking the BSY bit in the FLASH_SR register.
Check that no flash memory operation is in progress by checking the BSY bit in the FLASH_SR register (BSY is active when erase/program operation is going to bank 1 or bank 2). Check that no flash memory operation is in progress by checking the BSY bit in the FLASH_SR register (BSY is active when erase/program operation is in progress on bank 1 or bank 2).
Option bytes
- Description of user option bytes
- Programming user option bytes
- Read protection (RDP)
- Write protections
- Proprietary code readout protection (PCROP)
The Flash memory is organized in two banks of 512 Kbytes each (see Table 7: 1 Mbyte single bank Flash memory versus dual organization (STM32F42xxx and STM32F43xxx) and Table 9: Dual 1 Mbyte bank Flash memory organization ( STM32F42xx43xx3). The user area in the Flash memory can be protected from read operations with a trusted code. If an erase/program operation is attempted in a write-protected part of the Flash memory (sector protected by the write-protect bit, locked OTP portion or portion of Flash memory that can never be written as ICP), the write protect error flag (WRPERR) is set in the FLASH_SR register.
If an erase/program operation is performed to a write-protected area of the Flash memory, the Write Protection Error flag (WRPERR) is set in the FLASH_SR register. Flash memory user sectors (0 to 23) can be protected from D-bus read access using proprietary read-out protection (PCROP).
One-time programmable bytes
Flash interface registers
- Flash access control register (FLASH_ACR) for STM32F405xx/07xx and STM32F415xx/17xxfor STM32F405xx/07xx and STM32F415xx/17xx
- Flash access control register (FLASH_ACR) for STM32F42xxx and STM32F43xxxfor STM32F42xxx and STM32F43xxx
- Flash key register (FLASH_KEYR)
- Flash option key register (FLASH_OPTKEYR)
- Flash status register (FLASH_SR) for STM32F405xx/07xx and STM32F415xx/17xxSTM32F405xx/07xx and STM32F415xx/17xx
- Flash status register (FLASH_SR) for STM32F42xxx and STM32F43xxxSTM32F42xxx and STM32F43xxx
- Flash control register (FLASH_CR) for STM32F405xx/07xx and STM32F415xx/17xxSTM32F405xx/07xx and STM32F415xx/17xx
- Flash control register (FLASH_CR) for STM32F42xxx and STM32F43xxxSTM32F42xxx and STM32F43xxx
- Flash option control register (FLASH_OPTCR) for STM32F405xx/07xx and STM32F415xx/17xxSTM32F405xx/07xx and STM32F415xx/17xx
- Flash option control register (FLASH_OPTCR) for STM32F42xxx and STM32F43xxxfor STM32F42xxx and STM32F43xxx
- Flash option control register (FLASH_OPTCR1) for STM32F42xxx and STM32F43xxx for STM32F42xxx and STM32F43xxx
- Flash interface register map
These bits represent the ratio of the CPU clock period to the Flash memory access time. Set by hardware when the data to be programmed cannot be included in the same 128-bit Flash memory array. Set by hardware when an address to be erased/programmed belongs to a write-protected part of the Flash memory.
Set by hardware when one or more Flash memory operations (program/erase) are/are successfully completed. They can be written to program a new write protection or PCROP value into Flash memory.
4 CRC calculation unit
- CRC introduction
- CRC main features
- CRC functional description
- CRC registers
- Data register (CRC_DR)
- Independent data register (CRC_IDR)
- Control register (CRC_CR)
- CRC register map
Each write operation in the data register creates a combination of the previous CRC value and the new one (CRC calculation is done on the entire 32-bit data word, and not byte by byte). The write operation is stopped until the end of the CRC calculation, thus allowing back-to-back write accesses or consecutive write and read accesses. The CRC calculator can be reset to 0xFFFF FFFF with the RESET control bit in the CRC_CR register.
The CRC calculation unit contains two data registers and a control register. Periphery. CRC registers must be accessed in words (32 bits). This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register.
5 Power controller (PWR)
Power supplies
- Independent A/D converter supply and reference voltage
- Battery backup domain
- Voltage regulator for STM32F405xx/07xx and STM32F415xx/17xx
- Voltage regulator for STM32F42xxx and STM32F43xxx
Note: Overdrive and underdrive are not available when the regulator is bypassed. Set the ODSW bit in the PWR_CR register to switch the voltage regulator from normal mode to overdrive mode. Simultaneously reset the ODEN and ODSW bits in the PWR_CR register to switch the voltage regulator back to normal mode and disable Over-drive mode.
Reset the ODEN bit in the PWR_CR register to disable Overdrive mode. If the ODEN bit is reset instead, Overdrive mode is disabled and the voltage regulator is switched back to the initial voltage.
Power supply supervisor
- Power-on reset (POR)/power-down reset (PDR)
- Brownout reset (BOR)
- Programmable voltage detector (PVD)
Reset the ODSW bit in the PWR_CR register to switch the voltage regulator back to normal mode. Note: For full details of BOR characteristics, refer to the "Electrical Characteristics" section of the device's data sheet. You can use the PVD to monitor the VDD power supply by comparing it to a threshold selected by the PLS[2:0] bits in the PWR power control register (PWR_CR) for.
A PVDO flag is available in the PWR Power Control/Status Register (PWR_CSR) for the STM32F405xx/07xx and STM32F415xx/17xx that indicates whether VDD is above or below the PVD threshold. The PVD output interrupt can be generated when VDD falls below the PVD threshold and/or when VDD rises above the PVD threshold, depending on the EXTI line16 rising/falling edge configuration.
Low-power modes
- Slowing down system clocks
- Peripheral clock gating
- Sleep mode
- Stop mode (STM32F405xx/07xx and STM32F415xx/17xx)
- Stop mode (STM32F42xxx and STM32F43xxx)
- Standby mode
- Programming the RTC alternate functions to wake up the device from the Stop and Standby modesthe Stop and Standby modes
Sleep mode is entered by Section: Entering Low Power Mode, when the SLEEPDEEP bit in the Cortex®-M4 with FPU system control register is cleared. Entering Stop Mode (for STM32F405xx/07xx and STM32F415xx/17xx) Stop Mode is entered by section: Entering Low Power Mode, when the SLEEPDEEP bit in the Cortex®-M4 with FPU system control register is set. Stop mode is entered by Section: Entering Low Power Mode, when the SLEEPDEEP bit in the Cortex®-M4 with FPU system control register is set.
Standby mode is activated according to section: Entering power saving mode, when the SLEEPDEEP bit in the Cortex®-M4 with FPU system control register is set. The RTC provides a programmable time base to wake up from stop or standby mode at regular intervals.
Power control registers (STM32F405xx/07xx and STM32F415xx/17xx)STM32F415xx/17xx)
- PWR power control register (PWR_CR)
- PWR power control/status register (PWR_CSR) for STM32F405xx/07xx and STM32F415xx/17xxfor STM32F405xx/07xx and STM32F415xx/17xx
Note: This bit is not reset when the device wakes from standby mode, on a system reset, or on a power reset. Note: This bit is not reset when the device wakes from standby mode or on a system reset or power reset. For this reason, this bit is equal to 0 after Standby or Reset until the PVDE bit is set.
This bit is set by hardware and is only cleared by POR/PDR (power-on reset/power-down reset) or by setting the CSBF bit in the PWR_CR register. This bit is set by hardware and is cleared by system reset or by setting the CWUF bit in the PWR_CR register.
Power control registers (STM32F42xxx and STM32F43xxx) .1 PWR power control register (PWR_CR) .1 PWR power control register (PWR_CR)
- PWR power control/status register (PWR_CSR) for STM32F42xxx and STM32F43xxxfor STM32F42xxx and STM32F43xxx
These bits control the output voltage of the internal voltage regulator to provide a trade-off between performance and power consumption when the device is not operating at maximum frequency (refer to the STM32F42xx and STM32F43xx datasheets for more details). Note: This bit can only be set when operating on a supply voltage range of 2.7 to 3.6 V and when the Prefetch is OFF. If set, the flash memory will enter shutdown mode when the device enters stop mode.
When underrun mode is enabled, these bits are not set as long as the MCU has not yet entered stop mode. Note: An additional wakeup event is detected if the WKUP pin is enabled (by setting the EWUP bit) when the WKUP pin level is already high.
PWR register map
6 Reset and clock control for
STM32F42xxx and STM32F43xxx (RCC)
Reset
- System reset
- Power reset
- Backup domain reset
These sources act on the NRST pin and it is always held low during the delay phase. In case of an external reset, the reset pulse is generated while the NRST pin is asserted low. The Backup domain has two specific resets that affect only the Backup domain (see Figure 15).
When resetting the backup domain, all RTC registers and the RCC_BDCR register are set to their reset values. Software reset, activated by setting the BDRST bit in the RCC Backup domain control register (RCC_BDCR).
Clocks
- HSE clock
- HSI clock
- PLL configuration
- LSE clock
- LSI clock
- System clock (SYSCLK) selection
- Clock security system (CSS)
- RTC/AWU clock
- Watchdog clock
- Clock-out capability
- Internal/external clock measurement using TIM5/TIM11
The HSERDY flag in the RCC clock control register (RCC_CR) indicates whether the high-speed external oscillator is stable or not. The HSE crystal can be turned on and off using the HSEON bit in the RCC Clock Control Register (RCC_CR). The HSIRDY flag in the RCC clock control register (RCC_CR) indicates whether the HSI RC is stable or not.
The HSI RC can be turned on and off using the HSION bit in the RCC Clock Control Register (RCC_CR). The first output is used to generate the high-speed system clock (up to 180 MHz) – The second output is used to generate the clock for the USB OTG FS (48 MHz).
RCC registers
- RCC clock control register (RCC_CR)
PLLSAI OFF 1: PLLSAI ON
PLLI2S OFF 1: PLLI2S ON
PLL OFF 1: PLL ON
- RCC PLL configuration register (RCC_PLLCFGR)
When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware when an oscillator error is detected. This bit cannot be reset if the HSE oscillator is used directly or indirectly as a system clock. Set by hardware to turn ON the HSI oscillator upon exiting Stop or Standby mode or in the event of a failure of the HSE oscillator used directly or indirectly as a system clock.
Set and cleared by software to control the frequency of the USB OTG FS clock, the random number generator clock and the SDIO clock. Set and cleared by software to control the frequency of the common PLL output clock.
PLLP = 4 10: PLLP = 6
- RCC clock configuration register (RCC_CFGR)
- RCC clock interrupt register (RCC_CIR)
- RCC AHB1 peripheral reset register (RCC_AHB1RSTR)
- RCC AHB2 peripheral reset register (RCC_AHB2RSTR)
- RCC AHB3 peripheral reset register (RCC_AHB3RSTR)
- RCC APB1 peripheral reset register (RCC_APB1RSTR)
- RCC APB2 peripheral reset register (RCC_APB2RSTR)
- RCC AHB1 peripheral clock register (RCC_AHB1ENR)
- RCC AHB2 peripheral clock enable register (RCC_AHB2ENR)
- RCC AHB3 peripheral clock enable register (RCC_AHB3ENR)
- RCC APB1 peripheral clock enable register (RCC_APB1ENR)
- RCC APB2 peripheral clock enable register (RCC_APB2ENR)
- RCC AHB1 peripheral clock enable in low power mode register (RCC_AHB1LPENR)(RCC_AHB1LPENR)
- RCC AHB2 peripheral clock enable in low power mode register (RCC_AHB2LPENR)
- RCC AHB3 peripheral clock enable in low power mode register (RCC_AHB3LPENR)(RCC_AHB3LPENR)
- RCC APB1 peripheral clock enable in low power mode register (RCC_APB1LPENR)(RCC_APB1LPENR)
- RCC APB2 peripheral clock enabled in low power mode register (RCC_APB2LPENR)(RCC_APB2LPENR)
- RCC Backup domain control register (RCC_BDCR)
- RCC clock control & status register (RCC_CSR)
FMCLPEN: Flexible memory controller module clock enable during sleep mode This bit is set and cleared by software.
