Total-Ionizing-Dose Effects and Low-Frequency Noise

A typical noise waveform in the time domain [56]; (b) the schematic illustration of noise power spectral density in the frequency domain (after [57]). Normalized SVd as a function of frequency for 5-fin and 10-fin SOI (solid lines, S5 and S10) and bulk (dashed lines, B5 and B10) FinFETs with approximate β values shown in the inset. In contrast, bulk FinFETs tend to show increasing charge trapping with decreasing fin width, as a result of the electrostatic effects of nearby trapped charge in the STI [34], similar to trends observed in submicron bulk MOSFETs [18].

Low-frequency noise in the MOS devices

Origin of 1/f noise in MOS devices

An electron traveling from source to drain through the inversion layer of the Si substrate can be trapped in defects in the gate oxide located near the semiconductor-dielectric interface (boundary traps). Electrons trapped in the gate oxide reduce the net potential drop between the positively biased gate terminal and grounded substrate, reducing the effective gate voltage and consequently reducing the drain current. Since the capture/decapture process is stochastic and the number of carriers in the channel is large, it can significantly affect device performance.

Fig. I-2. The schematic illustration of 1/f noise origin in MOSFET due to gate oxide traps with different time constraints (after [55])

Temperature dependence of 1/f noise

1/f noise is formed by multiple switching events and if the distribution of the time constants of traps follows the rule D(τ) ̴ 1/τ for τ1<τ<τ2, so the shape of the 1/f noise is proportional to 1/f for 1/τ2

Total ionizing dose effects in MOS devices

Mechanism

Process of radiation-induced formation of interfaces and oxide traps described in the band diagram of a biased metal oxide-semiconductor structure [62].

Influence of irradiation on DC characteristics

Consequently, the effects of positive interface traps and positive oxide traps add up for pMOS device, increasing the absolute value of the negative threshold voltage, and shifting the IV curve negatively during TID exposure (i.e., increasing the radiation-induced threshold voltage shift) On the other hand, nMOS devices at the threshold are mostly affected by negatively charged traps located in the upper part of the Si band gap (filled acceptor-like traps), so for nMOS devices the effect of negatively charged interface traps compensates the negative radiation-induced threshold voltage shift due to always positive oxide traps Radiation-induced oxide trapped charge (green dash) and interface traps (red short dash) contributions on I-V curves in pMOSFET and nMOSFETs [62].

Fig. I-7. Schematic illustration of existing traps in the MOS device [16].

Influence of irradiation on 1/f noise

1/f noise versus temperature before and after irradiation and after high-temperature annealing of graphene transistors from [5].

Fig. I-10. 1/f noise vs temperature before and after irradiation and after high-temperature annealing of graphene transistors from [5]

Experimental details

Studied devices

During the experiments, the devices were connected in high-speed handmade packages shown in Fig.

Experimental setup

Irradiation
Low-frequency noise

During noise measurements, the drain voltage Vd was kept at 0.05 V with a source and substrate grounded. For low-frequency noise testing in a wide temperature range, a mounted unit was placed in the Janis VPF-100 Cryostat in a low-pressure environment. Random telegraph noise (RTN) measurements were performed at room temperature with a Keithley 4200-SCS Parameter Analyzer at the same bias conditions as 1/f noise measurements.

Fig. II-3. Schematic TID setup diagram (after [76]).

Impact of ionizing irradiation on DC characteristics

Bulk FinFETs

In the linear extrapolation method, the x-intercept of the linear extrapolation of the Id-Vg curve at the point of maximum transconductance gm with the Vg axis is defined as Vth + Vd/2 [79]. Threshold voltage shifts ΔVth as a function of irradiation and annealing time for large FinFETs with fin widths from 10 nm to 40 nm. The normalized maximum conductance gm_max shows an increase of less than 3% during irradiation for large FinFETs.

Normalized peak transconductance gm_max as a function of irradiation and annealing time for bulk FinFETs with fin widths from 10 nm to 40 nm. The narrowest devices show the largest increase in on-current of ∼12% versus ∼6% for wider devices, highlighting the relatively more significant influence of radiation-induced trapped charge in the SOI region in the modulating threshold voltage for narrow-fin devices. Increase in maximum drain current Ion (Vg = +0.8 V) as a function of irradiation and annealing time for bulk FinFETs with fin widths from 10 nm to 40 nm.

The relative difference in the influence of radiation-induced trapped charge and interface traps in narrow (left) and wide (right) bulk FinFETs is illustrated in Fig. and the trapped charge is more relaxed due to a relatively large front gate length. Here, the narrow-fin device has higher electric fields between the front gate and the charge trapped over a narrow subchannel region in the STI, which turns on a parasitic side transistor and enables a subchannel conduction leakage path [34].

Therefore, the influence of the trapped charge in the STI region near the channel is greater for the same accumulated dose in a device with a narrow rib than in a device with a wider rib.

Fig. III-2. Illustration of the leakage correction method [78].

SOI FinFETs

Id-Vg curves as a function of dose for SOI FinFETs with gate length of 30 nm and fin width of 10 nm;. Threshold voltage shift ΔVde as a function of irradiation and annealing time for SOI FinFETs with fin widths from 10 nm to 40 nm. The normalized peak transconductance gm_max decreases for 2-4% during irradiation for SOI FinFETs, which can be explained as increased carrier scattering by the radiation-induced interface and boundary traps.

In SOI devices no fringe width dependence is observed for the radiation-induced gm_max change. Normalized maximum transconductance gm_max as a function of irradiance and annealing time for SOI FinFETs with final widths from 10 nm to 40 nm. Increase in maximum Ion drain current (Vg = +0.8 V) as a function of irradiation and annealing time for SOI FinFETs with final widths from 10 nm to 40 nm.

To explain the fin width dependence on threshold voltage shifts ΔVth for SOI FinFETs, we need to discuss the influence of the lateral gates in these types of devices. Narrower fins in SOI devices with a smaller area under the channel improve the efficiency of lateral screening, resulting in remarkable radiation tolerance of narrow SOI FinFETs, which applies to a wide range of gate lengths [31]. The least radiation-induced degradation is observed for LG = 110 nm at lower doses and LG = 70 nm to 110 nm for higher doses.

The similar complicated gate length dependence was observed for NW SOI devices in [27], where it was simulated and attributed to the complicated distribution of charges in the subchannel region.

Fig. III-7. I d -V g curves as a function of dose for SOI FinFETs with gate length of 30 nm and fin width of 10 nm;

Discussion and Conclusions

In narrower and shorter channel transistors, the charge caused by radiation trapped in the STI more strongly affects the potential distribution in the subchannel region, lowering the barrier between source and drain, thus allowing carriers to transport between the terminals, increasing the subthreshold flow. due to band-to-band tunneling [82]. TID-induced normalized increase in off-state drain leakage for irradiated bulk FinFETs up to 0.5 Mrad as a function of fin width. The only significant differences are for the shorter, narrower devices, for which both RINCE and RISCE are observed due to electrostatic effects of charge trapped in the STI at Vthshifts and subthreshold stretching and leakage.

SOI devices proved their exceptional radiation tolerance up to a gate length of 30 nm, showing a reversal effect in threshold voltage shifts ΔVth and maximum drain current ION due to a combination of trapped charge in the BOX that dominates at low doses down to 0.5 Mrad (SiO2) and negatively charged interface traps and net negative trapped charge in the HfO2 gate oxide, predominant at higher doses. In all cases, the higher tolerance of narrower FinFETs is a result of the increased lateral gate control in narrow channel devices, which in turn provides efficient electrostatic control over the potential in the silicon body. Therefore, the coupling effects of the front and back gates are weakened and the effects of the trapped charges in the BOX are reduced [26], [32].

Fig. III-13. TID-induced normalized off-state drain leakage increase for bulk FinFETs irradiated up to 0.5 Mrad as a function of fin width

Impact of ionizing irradiation on 1/f noise

Room-temperature 1/f noise

Frequency dependence of SVd for SOI (square symbols) and bulk FinFET (circle symbols) before (filled symbols) and after (open symbols) irradiation. The inset shows the noise spectra 1/f before and after irradiation in the frequency range f = 1 Hz to 390 Hz. The angular frequency of the Lorentzian spectrum is ~ 30 Hz before irradiation and ~ 120 Hz after irradiation.

These results may reflect passivation of a pre-existing defect with a lower angular frequency and activation of a new defect with a higher angular frequency. Alternatively, small changes in position, energy, or bond angles with surrounding atoms, caused by nearby radiation-induced trapped charge, could have changed the observed frequency response due to the same defect. Spectra that deviate significantly from a 1/f shape due to significant contributions from RTN (e.g., Figure IV-3) are excluded from these specific comparisons.

At least some of these differences may be due to defects in near-channel BOX for the SOI devices [91]-[94] and near-channel STI for bulk FinFETs [87], [88]. After irradiation, the defect concentration in these devices is greater, leading to a higher noise power, and the defect-energy dependence is more uniform, with β ≈ 2.0. SOI and bulk FinFETs with fewer fins exhibit 3–10 times higher noise magnitudes than those with more fins, suggesting that some individual fins have higher than usual density of defects as processed [75] , [95] .

For 10-fin devices, these effects are relatively less important, because 1/f noise is inversely proportional to the effective fin width of the transistor [6].

Fig. IV-1. Frequency dependence of S Vd for SOI (square symbols) and bulk FinFETs (circle symbols) before (solid symbols) and after (open symbols) irradiation

Temperature dependence of 1/f noise

Bulk FinFETs
SOI FinFETs

Conclusions

Wang et al., “1/f noise in as-processed and proton-irradiated AlGaN/GaN HEMTs due to carrier number fluctuations,” IEEE Trans. Wang et al., “Radiation-induced charge trapping and low-frequency noise of graphene transistors,” IEEE Trans. Liang et al., “Defects and low-frequency noise in irradiated black phosphor MOSFETs with HfO2.

Song et al., “Fine Width and Bias Dependence of the Response of Three-Gate MOSFETs to Total Dose Irradiation,” IEEE Trans. Simoen et al., “Radiation effects in advanced multiple gate and silicon-on-insulator transistors,” IEEE Trans. El-Mamouni et al., “Heavy ion-induced current transitions in bulk and SOI FinFETs,” IEEE Trans.

Duan et al., “Bias Dependence of Total Toning Dose Effects in SiGe-MOS FinFETs,” IEEE Trans. Zhang et al., “Effects of total ionizing dose on strained Ge pMOS FinFETs on bulk Si,” IEEE Trans. Duan et al., “Effects of Negative Bias Temperature Instability on Low-Frequency Noise in SiGe pMOSFETs,” IEEE Trans.

Zhang et al., “Temperature dependence and post-irradiation annealing reaction of the 1/f noise of 4H-SiC MOSFETs,” IEEE Trans.