Chapter 2: Experimental Details
3.4. Device fabrication using CuPc as the active material
Till now, we studied the effect of thickness of the bilayer dielectric layer on the performance of the device using n– type organic semiconductor. We optimized the bilayer thickness for the better performance of the device at 100 nm PMMA and 10 nm Al2O3, which can provide low leakage current and high capacitance. In order to know whether these estimated dielectric thicknesses holds good for p-type semiconductors or not, we fabricated OFETs using CuPc as organic semiconductor. The ~60 nm thick CuPc film was deposited on the dielectric material at a substrate temperature of 80°C. CuPc has a HOMO level at ~5.3 eV, which is close to the Fermi level of the copper (Cu), and Cu is known to be used as a hole injection–electrode.28-29 The fabricated devices were characterized under vacuum conditions in an optically isolated Lake–Shore probe station to minimize the photocurrent. Interestingly, we obtained superior OFET characteristics for the optimized device structure (100 nm PMMA and 10 nm Al2O3).
Figure 3.11 (a) shows the schematic diagram of device structure with bilayer dielectric material and CuPc. The surface morphology of the CuPc deposited on bilayer dielectric material is shown in Figure 3.11 (b). The CuPc film exhibits a granular structure with slightly ellipsoidal grains of approximately 100 nm length along the long axis. Figure 3.11 (c & d) shows the output and transfer characteristic curves collected under vacuum conditions. The device
Bilayer gate dielectric system for the fabrication of OFETs 63 as shown in Figure 3.11 (c). The negative VGS is consistent with the hole accumulation. The hole saturation mobility of the device was calculated to be 0.004 cm2/Vs with VTh= – 2.4 V.
Figure 3.11. (a) Schematic illustration of the device fabricated with CuPc (b) CuPc deposited on bilayer PMMA (100 nm)/Al2O3 (10 nm) as dielectric, (c) Output characteristics curves and (d) transfer characteristics curves of OFET.
3.5. Stability of the OFET Device: Bias–Stress Effect
To find out the stability of the material, we performed the bias-stress measurement by applying constant value of VGS and VDS for the PTCDI–Br2–C18 and CuPc based devices. The IDS decay was high in the case of PTCDI–Br2–C18/SiO2 compared to bilayer dielectric material as shown in Figure 3.12 (a). In SiO2, the Si–OH groups (silonol) on the surface will act as electron traps and degrade the performance of the device under long-term bias-stress measurement. In the case of bilayer dielectric material, the interface traps are very low as calculated in the previous
3.12 (a). Figure 3.12 (b) shows the bias-stress measurement of the CuPc based device fabricated using the optimized structure. The decay of the IDS is only 30% after one hour of bias-stress, where as it was 50% in the case of PTCDI–Br2–C18 same dielectric material in addition to that, devices with CuPc active layer shown appreciable environmental stability.
OFETs with CuPc are more reliable even after treating with ambient for several days but the devices with PTCDI-Br2-C18 were completely degraded. Nevertheless, CuPc is a stable material and it can form closely compacted morphology as compared to PTCDI-Br2-C18. Because of these merits, we further used CuPc molecule to study the performance of the devices under different environmental conditions with the tri-layer gate dielectric system and those studies have been embedded in the remaining chapters.
Figure 3.12. (a) Bias-stress measurement of the device with PTCDI–Br2–C18 and different dielectric materials.
VGS=VDS=5V for bilayer, VGS=VDS=30V for SiO2. (b) Bias-stress measurement of CuPc device with optimized 100 nm PMMA and 10 nm Al2O3 bilayer as dielectric materials at VGS=VDS=– 7V.
3.6. Summary and Conclusions
PTCDI–Br2–C18 molecule was synthesized and used for the fabrication of OFETs. We have used a bilayer dielectric material containing PMMA and Al2O3 in the OFETs. An improved transistor performance with respect to operating voltage and mobility is obtained if PMMA is used as a passivation layer for the electrochemically grown aluminum oxide dielectric layer.
In order to achieve the highest carrier mobility with lower VTh, we have optimized the thickness
Bilayer gate dielectric system for the fabrication of OFETs 65 essentially controls the roughness of the film. This influences the interface states and increases with dielectric layer thickness. Devices fabricated with dielectric layer of PMMA(100 nm)/Al2O3(10 nm) were found to have higher field– effect mobility (~0.040 cm2/Vs) and lower VTh (~0.82 V). In addition, we have observed that the carrier mobility does not depend on the thickness of the dielectric layer. This has been attributed to the interfaces trap states, which are completely filled at the gate field below threshold voltages. Therefore, the charge carrier scattering by the trap states does not affect the carrier mobility in the linear and the saturation region of the OFET operation. Our measurements also demonstrated a way to determine the thicknesses of the dielectric layers for better processing conditions of OFETs. We also fabricated the CuPc devices with the optimized device geometry and device characteristics are greatly enhanced than n-type molecule based OFETs.
3.7. References
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12. Oh, J. H.; Liu, S.; Bao, Z.; Schmidt, R.; Wurthner, F. Air-Stable N-Channel Organic Thin-Film Transistors with High Field-Effect Mobility Based on N,N '- Bis(Heptafluorobutyl)3,4 : 9,10-Perylene Diimide. Appl. Phys. Lett. 2007, 91, 212107-3.
13. Briseno, A. L.; Mannsfeld, S. C. B.; Jenekhe, S. A.; Bao, Z.; Xia, Y. N. Introducing Organic Nanowire Transistors. Mater. Today 2008, 11, 38-47.
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15. Cao, X. Q.; Wu, Y. S.; Fu, H. B.; Yao, J. N. Self-Assembly of Perylenediimide Nanobelts and Their Size-Tunable Exciton Dynamic Properties. J. Phys. Chem. Lett. 2011, 2, 2163- 2167.
16. Geib, S., Zschieschang, U., Gsänger, M., Stolte, M., Würthner, F., Wadepohl, H., Klauk, H., Gade, L.H Core-Brominated Tetraazaperopyrenes as N-Channel Semiconductors for Organic Complementary Circuits on Flexible Substrates. Adv. Funct. Mater. 2013, 23, 3386-3874.
17. Zhan, X. W.; Facchetti, A.; Barlow, S.; Marks, T. J.; Ratner, M. A.; Wasielewski, M. R.;
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Bilayer gate dielectric system for the fabrication of OFETs 67 18. Perrin, L.; Hudhomme, P. Synthesis, Electrochemical and Optical Absorption Properties
of New Perylene-3,4:9,10-Bis(Dicarboximide) and Perylene-3,4:9,10-Bis (Benzimida zole) Derivatives. Eur. J. Org. Chem. 2011, 5427-5440.
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Effect of inner layer in tri-layer gate dielectric system on the performance of the OFETs 69
Chapter 4
Effect of Inner Layer in Tri-Layer Gate Dielectric System on the Performance of the OFETs
4.1. Introduction
The active performance of OFETs mainly depends on the nature of the organic semiconductor and on the polarity of organic/dielectric interface.1 In addition, a dielectric system plays a crucial role to determine the operational stability of the OFET. The stability of the drain current (IDS) during continuous operation is typically limited by the time-dependent trapping of accumulated charges into localized defect states in the semiconductor/dielectric interface. SiO2
is a promising inorganic dielectric material used for the fabrication of OFET because of its
high electrical strength and compatibility with silicon based microelectronic devices.2 However, various polymers have been investigated as gate dielectric materials in OFETs due to their low cost and easy processing conditions. Such materials include poly(vinyl alcohol)(PVA),3-4 poly(vinyl phenol)(PVP),5 polystyrene (PS),6 benzocyclobutene (BCB)7 and poly(methyl methacralate) (PMMA).8 Nevertheless, these polymer thin films generate high leakage current because of their low resistivity and low dielectric constant. In order to overcome the leakage currents one must use relatively thick polymer film, that results in to a low field-effect mobility and large threshold voltage. Most of the researchers have introduced the cross-linked polymers, bilayer organic/organic and organic/inorganic dielectric systems to resolve this issue and for improved performance of the OFETs.9-12 Among all polymer gate insulators, PVA is a promising candidate due to its high dielectric constant (k=9), smooth film forming capability13 and good resistive to most of the organic solvents.14 On the other hand, the PVA-based OFETs have been suffering from the relatively lower field-effect mobility and large hysteresis.15 This may be due to polar interface in the vicinity of the conducting channel and massive –OH functional groups in the PVA surface and bulk, that can easily capture moistures.16 Furthermore, PMMA contains hydrophobic methyl radical groups(–CH3),14 which plays a role as moisture inhibitors, as well as encouraging good ordering of the active organic layer as it is deposited on the surface. Therefore, very often multilayer dielectric systems contains two or more polymer dielectric materials are being used with a hydrophobic layer as top layer. For instance, She et al. used bilayer dielectric systems which contain PVA as bottom layer and PMMA, PS, PVN as the top layer.17 They studied that the performance of the OFET mainly depends on the top polymer layer. In this chapter we studied the effect of bottom layer on performance of the OFET.
However, the organic dielectric materials are very sensitive to the ambient conditions which effect the performance of the device during the operation. Therefore, the devices based on the polymer dielectric systems showed less stability under such conditions. Mainly, presence of – OH groups in the dielectric layer will destabilize the performance of the devices due to adsorbed water molecules from ambient.4, 18 In this aspect, various research groups put the efforts in order to reduce the density of the –OH groups present in the polymer dielectric
Effect of inner layer in tri-layer gate dielectric system on the performance of the OFETs 71 In this chapter, we report the exploitation of –OH functional groups present in the dielectric layer to enhance the carrier mobility and the stability of the OFETs. We have used a tri-layer dielectric system which consists of a polar layer sandwiched between a hydrophobic polymer layer and a high-k inorganic metal oxide (Al2O3) layer. There are two important reasons behind the choosing of an inorganic high-k dielectric layer, to overcome the leakage currents and to minimize the thickness of the polymer dielectric layers. When hydrophilic dielectric layer is separated from a semiconducting channel by a non-polar dielectric, the adsorbed water molecules do not come into direct contact with the –OH functional groups. Water molecules remain at the interface of semiconductor and hydrophobic dielectric layer. These water molecules are also polarized due to applied gate voltage and interact with the –OH functional groups through the non-polar layer. Additional charge accumulation was normally observed due to dipole polarization.23 In the presence of water molecules, –OH functional groups will be polarized much faster rate than before, resulting in enhanced device stability with almost hysteresis free operation. We have established this mechanism for the first time in our OFETs fabricated by CuPc as organic p-type semiconducting material. In order to elucidate the thorough understanding, we have chosen four distinguished dielectric materials, such as PMMA, PVA, PVP and PS. Where PVA or PVP contain polar –OH groups and PMMA and PS does not contain –OH groups.10, 17 In the device fabrication, these layers were capped with a hydrophobic PMMA layer, which is used to eliminate the migration of water molecule into the buried dielectric layer.24
4.2. Experimental Details
CuPc is one of the well-studied molecules in the phthalocyanine family, (purchased from Sigma-Aldrich) and used as an active material for the fabrication of tri-layer dielectric based OFETs. The typical CuPc molecular structure was shown in Figure 2.1 (a), which is about 1.26 nm. Here, four sets of transistors were fabricated using different polymer based bilayer dielectrics, such as PMMA, PMMA/PVA, PMMA/PVP and PMMA/PS in combination with anodized Al2O3 on glass substrates. PVA (MW =89000-98000 g/mol), PS (MW =170000 g/mol), PVP (MW= 25000 g/mol), and PMMA (MW = 5,50,000 g/mol) (Alfa-Aesar) were used without further purification.
4.2.1. Preparation of Gate Electrode and Anodization
Commercially available microscopic glass slides were chosen as the substrates instead of silicon wafers to reduce fabrication cost of the devices. The glass slides were sliced using diamond pen into 1cm × 2.5 cm sized pieces and cleaned as explained in the section 2.1.3. A
‘L’ shaped aluminium film (~200 nm thick) was deposited on the glass slide by thermal evaporation using the shadow masks. This aluminium pattern is functioned as the gate electrode. The film thickness was measured using surface profilometer. In order to reduce the leakage current and to minimize the thickness of the subsequent polymer dielectric layers, an Al2O3 ultrathin film was deposited on the Al surface by anodization technique.25-27 The complete process of galvanostatic anodization was explained in the section 2.1.6. The detailed experimental procedure for optimizing the thickness of Al2O3 and PMMA was discussed in chapter 3.
4.2.2. Spin-Coating of Polymer Dielectric Layers
Anodized Al2O3 surfaces were found to be rough with typical rms roughness in the range of 10 nm-20 nm.26 In order to achieve a smooth interface between gate dielectric and organic channel, we have spin-coated PMMA, PVA, PVP, PS layers on the Al2O3 surfaces. A set of polymer solutions were prepared by dissolving 30 mg/mL PVA in de-ionized water, 30 mg/mL PS in toluene and 30 mg/mL PVP in freshly dried and distilled Tetrahydrofuran (THF).
Anodized substrates were spin coated by pre-prepared polymer solutions at 3000 rpm for 60 seconds and annealed at 100 °C for 1h in vacuum oven. The thickness of the individual polymer layer was optimized to ~70 nm. Subsequently, all the thin films were spin coated by about 30 nm thick PMMA film as second layer and vacuum annealed at 100°C for 1 h. The morphology of the individual dielectric films was characterized by AFM. The fabricated four sets of devices containing tri-layer gate dielectrics system composed of PMMA (30 nm)/X(70 nm)/Al2O3(10 nm), with layer X indicating PMMA, PVA, PS and PVP. The corresponding devices are named as A, B, C and D devices, respectively. The schematic illustration of the device was described in Figure 4.1.
Effect of inner layer in tri-layer gate dielectric system on the performance of the OFETs 73 4.2.3. CuPc Molecule and Source/Drain Electrodes Deposition
High quality CuPc films were deposited on the stack of tri-layer dielectrics by custom-designed thermal evaporator, which is equipped with substrate holder, heater and rotator. At first the chamber was evacuated to a base pressure of ~10−7 mbar using a turbo molecular pump. CuPc molecules were evaporated at 80 °C substrate temperature with a deposition rate of 0.03 nm/sec. The CuPc deposition rate was probed by a quartz crystal monitor (QCM), which was calibrated by a surface profilometer (Veeco Dektak 150) in advance. The fabricated OFETs are bottom contact device having CuPc thin film thickness of ~60 nm. The surface morphology of the deposited films are characterized by tapping mode AFM. The AFM images were processed and analyzed by using Nanotech software package (WSxM 5.0 Develop 7.0).28
Figure 4.1. The schematic shows a typical OFET design with a tri-layer organic-inorganic gate dielectric interface. Note: The thickness of each layer is displayed at the right side of the figure. Four separate devices are fabricated with different organic dielectrics, such as PMMA/PMMA, PMMA/PVA, PMMA/PS and PMMA/PVP, along with the anodized Al2O3 layer. The symbol ‘X’ in the schematic denotes the dielectric layers used for each OFET device fabrication.
A schematic of the OFET that consists of top-contact and bottom-gate geometry is shown in Figure 4.1. Copper (Cu) source (S) and drain (D) electrodes were deposited by thermal evaporation using shadow masks. The typical channel width (W) and length (L) of the OFETs
(~1×10-4 mbar) as well as under ambient (65% relative humidity (RH)) conditions. OFET devices were characterized using a lakeshore probe station interfaced to a Keithley 4200 semiconductor characterization system (SCS).
4.3. Results and Discussion
4.3.1. Surface Morphology of Aluminium Gate and Alumina
Figure 4.2 shows a typical AFM topography images of aluminium thin film (gate) deposited on a glass slide at room temperatures, before and after anodization. A high-density of Al grains have been formed within the Al film as shown in Figure 4.2 (a) having the rms roughness ~3.25 nm. We have observed an increment in the surface roughness (6.45 nm) and grain size of the films after 10 nm anodization, as depicted in the Figure 4.2 (b). The possible reason for the increment in the roughness of the top surface might be due to the formation of porous oxide layer underlying dense barrier layer during the anodization process.29 The rms roughness of the film depends on the formation current density, applied voltage, anodization time and the concentration of the electrolyte solution.
Figure 4.2. AFM topography images showing the surface morphology and uniformity of (a) as deposited aluminium film (before anodization) on glass substrate (b) 10 nm thick anodized alumina surface (after anodization). The surface roughness becomes double after anodization.
4.3.2. Surface Morphology of Polymer Dielectric Materials
Further the morphological features of the polymer dielectric layers were extensively