In order to investigate the performance of the proposed FTCO-ABSC scheme, a prototype of DC- DC buck converter as discussed in subsection 2.3.4 of Chapter 2, equipped with the closed loop control is made with following specification. Supply DC voltageE = 25V, filter inductor,L= 59mH, inductor resistance rL = 4.54Ω, capacitor C = 220µF,450V rating, nominal load resistance R = 20Ω, refer- ence output voltage vr = 10V and switching frequency fs = 20kHz. Further the selected controller parameters are adaptive gain γ = 9×10−5, observer rate λ1 = 0.05, λ2 = 0.5, observer parameter
5.4 Experimental Results and Discussion
ε = 0.05 and backstepping gains c1 = 6000, c2 = 20. To investigate the performance and robust- ness, the proposed control scheme is applied to the DC-DC buck converter system under different test conditions as described below. The proposed FTCO-ABSC is also evaluated against conventional adaptive backstepping control (ABSC) procedure [91] under identical experimental conditions. The tests conducted are the following:
Test 1: Step change in reference voltage from 0−10V
The transient performance of output voltage vo and inductor current iL in response to the reference voltage vr = 10V during start-up are evaluated in Figure 5.2. Figure 5.2 (a) demonstrates the re- sponses of converter states under ABSC control. The output voltage takes 28ms to reach the desired reference, besides suffering from 2V peak-to-peak ripple voltage in the steady state. The correspond- ing response ofiL can be observed in Figure 5.2 (a). In the contrary, the proposed FTCO-ABSC in Figure 5.2 (b) provides a quick start-up within 15msand a clean output voltage profile with negligible ripple. However, the inductor current shows a peak in initial phase while reaching the nominal current of 0.5A. Also, it must be noted that the peak-to-peak ripple in the output vo under the action of proposed FTCO-ABSC method is 0.3V, in contrast to 0.7V ripple offered by ABSC scheme.
Test 2: Sudden change in input voltage E from 25V to 17V and vice-versa.
The effectiveness of the proposed control under a matched uncertainty is examined in this test. After the steady state is reached, the DC-DC buck converter is exposed to a sudden source voltage change scenario. The input voltage E is suddenly perturbed from the nominal 25V to 17V and vice-versa, amounting to 32% input voltage disturbance. The performances ofvo andiL under ABSC in response to source voltage change are shown in Figure 5.2 (c). The result shows that during the input change from 25V to 17V, the conventional ABSC yields a large undershoot of 50% and reaches 5V level. The time taken to reject input disturbance is observed to be 70ms. Similarly, the change of input voltage from 17V to nominal 25V produces a 50% overshoot with a settling time of 70mswhile tracking the set 10V reference voltage. Corresponding inductor current exhibits high undershoot and overshoot.
On the other hand, the performance of the proposed FTCO-ABSC strategy in 5.2 (d) is satisfactory and yields no undershoot and overshoot. Subsequently, the inductor current exhibits a cleaner profile.
Test 3: Sudden change in load resistance R from 20Ω to 10Ω and vice-versa.
The robustness of the proposed control is next investigated under widely varying load conditions.
Figure 5.3 (a) and 5.3 (b) reveal the converter response for the loading test, under whichR changes from 20Ω to 10Ω, amounting to 50% change. The ABSC method produces an undershoot of 45% invo
and reaches the level of 5.5V. In addition, the time recorded to reject such a mismatched uncertainty is noted to be 85ms. Similarly, during the unloading test,Rchanges from 10Ω to 20Ω. The ABSC shows a high overshoot of 17V, accounting to a 70% peak and convergence time of 90ms. Interestingly, under the proposed FTCO-ABSC scheme, the output voltage demonstrates a robust and accurate immediate tracking of desired reference voltage. The response obtained in the proposed method is devoid of any overshoot and undershoot during both loading and unloading conditions. Subsequently, the inductor current response in also found to be satisfactory.
(a) (b)
(c) (d)
Figure 5.2: Experimental response curves of DC-DC buck converter: (a) ABSC: output voltage vo and inductor current iL during start up (scale: x-axis; time (50ms/div), y-axis; voltage (5V/div) and current (500mA/div)), (b) proposed FTCO-ABSC: output voltage vo and inductor current iL during start up (scale:
x-axis; time (200ms/div), y-axis; voltage (5V/div) and current (500mA/div)), (c) ABSC: output voltagevoand inductor current iL during a step change in input voltage, E from 25V to 17V and vice-versa (scale: x-axis;
time (500ms/div), y-axis; voltage (5V/div) and current (500mA/div)) and (d) proposed FTCO-ABSC: output voltage vo and inductor current iL during a step change in input voltageE from 25V to 17V and vice-versa (scale: x-axis; time (500ms/div), y-axis; voltage (5V/div) and current (500mA/div)).
Remark 12. In Figure 5.2 (a), the output voltage profile under the operation of ABSC exhibits oscillations with peak to peak ripple of 0.85V across the desired 10V output. These oscillations may be due to sensor noise.
Test 4: Reference voltage change from 10V −15V.
Lastly, to investigate the response speed of the proposed control algorithm, vr is suddenly changed from nominal 10V to 15. The transient response obtained with ABSC mechanism is shown in Figure 5.3 (c). Initially the ABSC response is observed to be faster. However, it takes nearly 200mstime to converge to the new reference voltage of 15V. On the contrary, the proposed control in Figure 5.3 (d) yields a rapid response of vo in 5ms. The inductor current dynamics show an overshoot during the
5.4 Experimental Results and Discussion
(a) (b)
(c) (d)
Figure 5.3: Experimental response curves of DC-DC buck converter: (a) ABSC: output voltage vo and inductor currentiL during a step change in load resistanceR from 20Ω to 10Ω and vice-versa (scale: x-axis;
time (500ms/div), y-axis; voltage (5V/div) and current (500mA/div)), (b) proposed FTCO-ABSC: output voltagevo and inductor current iL during a step change in load resistance R from 20Ω to 10Ω and vice-versa (scale: x-axis; time (500ms/div), y-axis; voltage (5V/div) and current (500mA/div)), (c) ABSC: output voltage voand inductor currentiL during a step change invrfrom 10V to 15V (scale: x-axis; time (500ms/div), y-axis;
voltage (5V/div) and current (500mA/div)) and (d) proposed FTCO-ABSC: output voltagevo and inductor currentiLduring a step change invrfrom 10V to 15V (scale: x-axis; time (50ms/div), y-axis; voltage (5V/div) and current (500mA/div)).
The experiments investigated have shown that the proposed FTCO-ABSC strategy is capable to provide a strict output voltage regulation for a wide range of perturbations under both matched and mismatched conditions. The spikes produced in the inductor current profile during reference voltage change are a result of dependency of error variables z1 and z2 on the derivative of current estimation error ˜ξ2 and the same may be tolerated by slight increase in the power handling capability of the converter.