Modifications leading to different CNOT error distributions

1.5 Actual Implementation and architectural constraints

1.5.3 Modifications leading to different CNOT error distributions

We have discussed possible modifications to reduce gate count of the circuit for preparing the Dicke state|Dⁿ_ki and have also seen how these modifications affect the error induced in the circuit with

Circuit Backend Fidelity C_4,2,Cb_4,2 Simulator 1

C_4,2 “ibmqx2” ≈0.40 trans(C_4,2) “ibmqx2” ≈0.43 Cb_4,2 “ibmqx2” ≈0.53

Table 1.4: Fidelity of|D₂⁴iprepared using different circuits on 20/09/2021 Circuit Backend Fidelity

C_4,2,Cb_4,2 Simulator 1 C_4,2 “ibmqx2” ≈0.25 trans(C_4,2) “ibmqx2” ≈0.35 Cb_4,2 “ibmqx2” ≈0.40

Table 1.5: Fidelity of|D₂⁴iprepared using different circuits on 04/11/2021

Figure 1.14: Density matrix corresponding to |D₂⁴i when run in simulator

Figure 1.15: Density matrix corresponding to Cb_4,2 corresponding to the result in Table 1.5

respect to the “ imbqx2” machine provided by IBM-QX. The main tool behind these modifications were identification and analysis of different partially defined unitary transformations.

Let us now shift our focus to observing how these partially defined transformations can also

come in handy when analyzing the expected amount of noise affecting a circuit. We describe this scenario with the case study of Cb_4,2. Consider a four qubit architecture A4 that has the same CNOT connectivity asG^Cb4,2 and only differs in CNOT error distribution. We will now observe how further modifying the circuitCb_4,2 can lead to lower CNOT error on expectation against some error distributions in the architectureA₄. We assume every edge in the CNOT map ofA₄is bidirectional, as is the case with all currently publicly available IBM-Q machines. The CNOT error rate when applying a CNOT between qubits iand j (such that the edge i↔ j is present in G_A) is denoted ase_ij.Figure 1.17 shows the CNOT map of the architecture.

CNOT error model

In this regard let us define a plausible error model to calculate CNOT error on expectation of a circuit implemented in the architectureA₄. The probability of a CNOT placed between qubitsiand jacting erroneously in a circuit is dependent on the error rate of the corresponding CNOT coupling in the architecture. We call this CNOT error. We denote this probability with f_e: [0,1]→ [0,1].

We do not assume the exact nature of fe, but only that it is a monotonically increasing function w.r.t to CNOT error rate which is by definition.

Next we define the following Bernoulli random variables to calculate the the number of CNOT acting erroneously on expectation when a circuit is applied on this architecture. We define a variable x_k corresponding to each CNOT used in a circuit. The variable is assigned zero if the k-th CNOT is applied correctly while executing a circuit, and one otherwise.

Let us suppose thek-th CNOT is applied between qubits iandj. Then we haveP r(x_k= 1) = f_e(e_ij) and The expected error while applying the CNOT isE(x_k) =f_e(e_ij). Therefore the CNOT error on expectation while implementing a circuit C on the architecture is

E(C) =X

v_ijf_e(e_ij).

Having described the error model we look at the CNOT distribution of the circuit Cb_4,2 as a weighted graph G_f. The vertices and the edges of this graph is same as that ofG^Cb4,2. The weight of an edge qi ↔ qj is the number of CNOT gates applied between the two qubits in the circuit.

The graphG_f is shown in Figure 1.16.

Now we implement the circuit Cb_4,2 on the architectureA4 so that all CNOT constraints can be

met. We observe that only the qubit 1 has degree 3 and therefore q₁ is mapped to the physical qubit 1. Then we can have the following maps which satisfies all the CNOT constraints.

1. q₁ →1,q₀ →0,q₂ →2,q₃ →3. 2. q₁ →1,q₀ →2,q₂ →0,q₃ →3.

Then the expected CNOT error of the circuitCb_4,2 when applied on the architecture A₄ is

E(Cb_4,2) = 5f_e(e₀₁) + 3f_e(e₀₂) + 3f_e(e₁₂) +f_e(e₁₃).

Now let us observe how the circuit Cb_4,2 (described in Figure 1.10) can be further modified using partially defined transformations so that the CNOT error in the circuit on this architecture will reduce on expectation under some error distribution conditions.

q₀ q₁

q₂ q₃ 5

3 1

3

Figure 1.16: Graph G_f corre- sponding to G^Cb4,2.

0 1

2 3

e01

e₁₂ e₁₃ e₀₂

Figure 1.17: CNOT map of the architecture A.

q₀ q₁

q₂ q₃ 5 3

1 3

Figure 1.18: Graph G⁰_f corre- sponding to Cb_4,2⁰

|0i • ^−θ32

4

θ₃² 4

−θ²₃ 4

θ²₃

4 • • ^π

2 −^θ₂¹² −(^π₂ −^θ₂²¹) •

|0i θ₄² • ^π

2 −^θ₂³¹ −(^π₂ −^θ₂¹³) • • •

|0i X • • • •

|0i

Figure 1.19: Circuit description ofCb_4,2⁰

The firstR_y gate that acts on the second qubit of Cb_4,2 is followed by the CNOT gatesCNOT²₃ and CNOT²₄. The combined transformation T4 of these two CNOT is defined only for two basis states on 4 qubits |0011i → |0011i and |0111i → |0100i.

We can use the partial nature of the transformation to modify the circuit as follows. Note that transformationT4 is the first transformation that acts on q3. Then if we start the circuit from the

state|0010i instead of|0011ithen we can define the transformation T₄¹ such that T₄¹≡(I₂⊗CNOT³₂⊗I₂)(I₂⊗I₂⊗CNOT²₁)

=⇒T₄¹|0010i=|0011i, T₄¹|0110i=|0100i

resulting in the same output states as T₄ for all the computational basis states for which T₄ is defined. It is important to note that this implementation would not have been possible if the transformation was defined for all the 8 basis states of the second third and fourth qubits.

Let’s denote this circuit as Cb_4,2⁰ and it is drawn in Figure 1.19. The weighted CNOT map of the circuitCb_4,2⁰ is denoted as asG⁰_f and it is shown in Figure 1.18.

Now observe that in the graph G⁰_f ,q2 has degree three and therefore any map that meets all the CNOT constraints will have q₂ → 1. Therefore we can have the following maps that satisfies all the CNOT constraints.

1. q₂ →1, q₀ →0, q₁→2, q₃ →3. 2. q₂ →1, q₀ →2, q₁→0, q₃ →3.

The CNOT error on expectation for both the circuits is

E(Cb_4,2⁰ ) = 5fe(e02) + 3fe(e01) + 3fe(e12) +fe(e13).

Now we calculate the conditions when E(Cb_4,2⁰ ) is less thanE(Cb_4,2⁰ ).

E(Cb⁰_4,2)<E(Cb_4,2)

=⇒5f_e(e₀₂) + 3f_e(e₀₁) + 3f_e(e₁₂) +f_e(e₁₃)

<5f_e(e₀₁) + 3f_e(e₀₂) + 3f_e(e₁₂) +f_e(e₁₃)

=⇒f_e(e₀₂)< f_e(e₀₁)

=⇒e₀₂< e₀₁.

This gives us an insight into how different CNOT distributions in a circuit may lead to better results without reduction in the number of CNOT gates or a reduction in the architectural constraints.

We conclude this section by describing the architectural constraint of the circuit Cb_n,k. Here note that this CNOT error model is rather simplistic and we design this model to emphasize how the

distribution of the CNOT gates in the circuit is also of importance in trying to reduce the error due to the noise in the system. One can refer to [14] to get a more formal approach towards noise aware circuit compilation.