International Journal of Recent Advances in Engineering & Technology (IJRAET)
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AHB interfaced High Speed DDR SDRAM Memory Controller
1D. Ramya Sree, 2K. Ragini
1M.Tech, Department of ECE, M.Tech, Department of ECE, Hyderabad, India,
2Professor, Department of ECE GNITS Hyderabad, India
Abstract—In the today’s world of fast emerging technologies, memory access speed is the pressing parameter that is being looked into. This results in the need for faster and larger memories. The clock speed is to be increased to improve the access speed, which implies design complexity. But using a DDR SDRAM improves the speed by two times with the same memory configuration.
Instead of processor directly accessing the memory, memory controllers are designed. A memory controller contains the logic to control the flow of data from and to the memory. The processor has to be in idle state till the controller fetches the data from memory. So, in this paper, we have targeted for a DDR SDRAM memory controller, with memory queues. With this architecture, cache model reads and queue model writes are implemented. So, the controller need not search the actual memory for the requested data, which makes the memory access to the processor easier and faster. This controller is designed specifically for AHB which has a high throughput. AHB supports the efficient connection of processors, on-chip memories and off-chip external memory interfaces with low-power peripherals. This improves the overall efficiency of the system.
Keywords—DDR SDRAM; memory; cache model, queues;
AHB
I. INTRODUCTION
The need for high speed and high performance made memories to operate at the maximum clock rate possible. But the increase in the clock increases the design complexity. So the DDR memories came into existence. The memory hierarchy can be discussed as below.
A DRAM consists of a transistor and a capacitor to store a single bit of data. The charge on the capacitor degrades continuously with time. So it requires a refresh circuit.
SDRAM is a DRAM circuit that is synchronized with the system bus, and carries data on the rising edge of clock. The DDR SDRAM is a JEDEC standard, in which data transfer occurs both at the rising and falling edges of the clock. When compared to SDRAM DDRSDRAM transfers data two times faster.
To further organize the data transfer memory controllers are designed. A memory controller consists of a refresh
circuit and a digital circuitry that controls the data flow to and from the memory. This paper is targeted for DDR SDRAM memory controller, which on one side has an interface for AHB and for DDR SDRAM on the other side. This proposed design with memory queues improves the speed by organizing the latencies due to the memory operations.
II. LITERATURE SURVEY
A. Double Data Rate SDRAM
JESD79C, is the JEDEC standard for DDR SDRAM specifications [1]. This is one of the new standards to replace SDRAM. DDR achieves nearly twice the bandwidth compared to SDRAM with the phenomenon of double pumping. Thus the DDR makes higher transfer rates possible with the same clock and data signals by strict control of timing. DDR supports both error correction and non- parity data transfers.
B. AMBA – AHB
The Advanced Microcontroller Bus Architecture (AMBA) specification defines an on chip communications standard for designing high- performance embedded microcontrollers. AMBA (Advanced Microcontroller Bus Architecture), is a bus standard devised by ARM with aim to support efficient on-chip communications among ARM processor cores.
Nowadays, AMBA is one of the leading on-chip busing systems used in high performance SoC design. AMBA is hierarchically organized into two bus segments, system- and peripheral-bus, mutually connected via bridge that FIFO data operations between them.
Standard bus protocols for connecting on-chip components generalized for different SoC structures, independent of the processor type, are defined by AMBA specifications. AMBA does not define method of arbitration. Instead it allows the arbiter to be designed to best suit the applications needs. It is used as the on- chip bus in system-on-a-chip (SoC) designs. Since its inception, the scope of AMBA has gone far beyond microcontroller devices, and is now widely used on a range of ASIC and SoC parts including applications
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processors used in modern portable mobile devices like smartphones. The AMBA protocol is an open standard, on-chip interconnect specification for the connection and management of functional blocks in a System-on-Chip.
The three distinct buses specified within the AMBA bus are
Advanced High-performance Bus (AHB)
Advanced System Bus (ASB)
Advanced Peripheral Bus (APB)
a) AHB
AHB is a new generation of AMBA bus which is intended to address the requirements of high- performance synthesizable designs. It is a high- performance system bus that supports multiple bus masters and provides high-bandwidth operation. AHB is for high clock frequency system modules. It acts as the high-performance system backbone bus. AHB supports the efficient connection of processors, on-chip memories and off-chip external memory interfaces with low-power peripherals.
AMBA AHB implements the features required for high- performance, high clock frequency systems including:
burst transfers
Pipelined operation
Multiple bus masters
split transactions
wider data bus configurations (64/128 bits)
Bridging between this higher level of bus and the current ASB/APB can be done efficiently to ensure that any existing designs can be easily integrated. An AMBA AHB design may contain one or more bus masters, typically a system would contain at least the processor and test interface. However, it would also be common for a Direct Memory Access (DMA) or Digital Signal Processor (DSP) to be included as bus masters.
The external memory interface, APB Bridge and any internal memory are the most common AHB slaves. Any other peripheral in the system could also be included as an AHB slave. However, low-bandwidth peripherals typically reside on the APB. A typical AMBA AHB system design contains the following components. A bus master which is able to initiate read and write operations by providing an address and control information. Only
one bus master is allowed to actively use the bus at any one time.
A bus slave which responds to a read or write operation within a given address-space range. The bus slave signals back to the active master the success, failure or waiting of the data transfer. The bus arbiter ensures that only one bus master at a time is allowed to initiate data transfers.
Even though the arbitration protocol is fixed, any arbitration algorithm, such as highest priority or fair access can be implemented depending on the application requirements and the AHB decoder is used to decode the address of each transfer and provide a select signal for the slave that is involved in the transfer.
AHB signal prefixes: H indicates an AHB signal. For example, HREADY is the signal used to indicate that the data portion of an AHB transfer can complete. It is active HIGH.
C. Geniric Memory Controller with AHB Interface A memory controller basically consist of two main sub parts, command generator, command scheduler.
Command generator generates the command required for the operation and a scheduler schedules each command being issued by command generator to the memory. In addition, the arbiter issues bus grant or busy signlas.
Fig. 1. Architecture of a Generic Memory Controller
III. OVERVEIW AND IMPLEMENTATION
As shown in Fig 2, the controller has to synchronize data transfers between the memory and the processor. To maintain this, the controller has to take the instructions on the bus and convert them back to an instruction suitable to the DDR. So the bus has to be put in hold till the instruction is processed by the memory, since the memory and processor have different speeds. This makes the throughput of entire system low. So, to increase the throughput, we have stored the data to be read or written in the local memory of the controller in the form of queues. The write instructions on the bus are queued up in the write memory queues, making the bus free so that the processor can use it for other purposes.
When the AHB gives a read instruction, the memory controller brings the block of data from the memory a
places in its read memory queues based on the principle of temporal and special locality. This helps in fetching the data without actually searching the DDR. This model of memory controller reduces the number of clock cycles required for fetching the data from DDR.
Synchronization is also provided between the read and write local memories of the controller to ensure data accuracy.
A. DDR SDRAM - OPERATION
DDR has four control signals and three command signals. The control signals are
CKE – Clock Enable
Csb – Chip Select
DQ – Data Lines
DQM – Data Mask
Fig. 2. Complete System Architecture The command signals are
Rasb – Row Address Strobe
Casb – Column Address Strobe
Web – Write Enable
The memory operations of DDR is controlled by the above signals. Based on this the DDR can be in three states as listed in Table I.
As shown in Fig. 3, DDR goes into active state from idle state on the issue of an active command. The activated row is then precharged after a read or write instruction, to save the data in the row back to the memory.
Fig. 3. DDR State Machine
Temporization is another characteristic of DDR memories. Memory temporization is given through a series of numbers, such as 2-3-2-6-T1, 3-4-4-8 or 2-2-2- 5 for DDR. These numbers indicate the number of clock pulses that it takes the memory to perform a certain operation. The smaller the number, the faster the memory. The operation that these numbers represent are the following : CL–tRCD–tRP–tRAS–CMD. To understand them, remember that the memory is internally organized as a matrix, where the data is stored at the intersection of the rows and columns.
CL: Column address strobe (CAS) latency is the time it takes between the processor asking memory for data and memory returning it.
tRCD: Row address strobe (RAS) to CAS delay is the time it takes between the activation of the row (RAS) and the column (CAS) where data is stored in the matrix.
TABLE I. DDROPERATION
Function
Signals
Cs Rasb Casb Web Address
Active L L H H Row
Read L H H H Col
Write L H L L Col
Precharge L L H L row
tRP: RAS precharge is the time between disabling the access to a row of data and the beginning of the access to another row of data.
tRAS: Active to precharge delay is how long the memory has to wait until the next access to memory can be initiated.
CMD: Command rate is the time between the memory chip activation and when the first command may be sent to the memory. Sometimes this value is not informed. It usually is T1 (1 clock speed) or T2 (2 clock speeds)
To handle the above mentioned latencies, memory controller with memory queues is focused in this paper.
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Read and write access to the DDR is burst oriented;
access start at a selected location and continue for a programmed number of locations in a programmed sequence. Access begin with the ACTIVE command, which may then be followed by a READ or WRITE command. The address bits issued coincident with the ACTIVE command are used to select row to be accessed. This row is placed in the row buffer, which is a sense amplifier. The address bits registered coincident with the READ or WRITE command are used to start the column location for the burst access. The DDR provides programmable READ or WRITE burst lengths of 2, 4, or 8 locations. As similar to the standard SDRAMs, pipelined architecture of DDR allows for concurrent operation, thereby providing high effective bandwidth by hiding row pre-charge and activation time.
B. AHB Operation
AHB is a new generation of AMBA bus which is intended to address the requirements of high- performance synthesizable designs. It is a high- performance system bus that supports multiple bus masters and provides high-bandwidth operation. AMBA AHB implements the features required for high- performance, high clock frequency systems including:
Bridging between this higher level of bus and the current ASB/APB can be done efficiently to ensure that any existing designs can be easily integrated. An AMBA AHB design may contain one or more bus masters, typically a system would contain at least the processor and test interface. However, it would also be common for a Direct Memory Access (DMA) or Digital Signal Processor (DSP) to be included as bus masters. Refer [4].
Overview of AHB operation
Before an AHB transfer can commence the bus master must be granted access to the bus. This process is started by the master asserting a request signal to the arbiter.
Then the arbiter indicates when the master will be granted use of the bus. A granted bus master starts an AHB transfer by driving the address and control signals.
These signals provide information on the address, width of the transfer, as well as an indication if the transfer forms part of a burst. A write data bus is used to move data from the master to a slave, while a read data bus is used to move data from a slave to the master. Every transfer consists of an address and control cycle [4].
The address cannot be extended and therefore all slaves must sample the address during his time. The data, however, can be extended using the HREADY signal.
When LOW this signal causes wait states to be inserted into the transfer and allows extra time for the slave to provide or sample data. During a transfer the slave shows the status using the response signals, HRESP [1:0].
OKAY (00) - OKAY response is used to indicate that the transfer is progressing normally and when HREADY goes HIGH this shows the transfer has completed successfully.
ERROR (01) - The ERROR response indicates that a transfer error has occurred and the transfer has been unsuccessful.
RETRY (10) - A RETRY indicates the transfer is not successful, so send the same again.
SPLIT (11) - SPLIT response indicates, to send the data from the point where it has broken the last.
a) Basic Transfer
An AHB transfer consists of two distinct sections:
The address phase, which lasts only a single cycle.
The data phase, which may require several cycles.
This is achieved using the READY signal.
The master drives the address and control signals onto the bus after the rising edge of HCLK.
The slave then samples the address and control information on the next rising edge of the clock.
C. Operation of DDR SDRAM Controller a) Without Local Memory
Only one row in an active bank can be accessed. An ACTIVE command can open a row and make active the particular row in the memory. A PRECHARGE command issued to memory can set the SDRAM to idle state, i.e. closing the open row in this memory.
Fig. 4. AHB Basic Transfer
If every time after accessing a row AUTOPRECHARGE command is performed, and the next access is actually involving the same row of the same bank, an ACTIVE command needs to be applied again in order to access
the last open row .As it is known that time needed between ACTIVE and READ/WRITE commands has to be fulfilled. In a successive period of time a program probably only accesses a small part of continuous address space. So that it is not necessary to issue an AUTO-PRECHARGE command after every read/write access without judging if there’s any need. If the current access is for an open row in an active bank, the READ or WRITE command is directly issued to the SDRAM, the ACTIVE and READ or WRITE commands. When the auto-refresh is required, all the active banks will be inactivated by applying PRECHARGE ALL command as auto-refresh can only be issued when the whole SDRAM is in idle state. In this way, the overhead caused by frequently opening and closing the DDR banks can be decreased.
b) With the local memory
The operation of the memory controller remains the same. But in this case we have provided 8 queues, 4 for read and 4 for write, in the memory controller, to queue up the instructions issued by the processor. The write queues can store up to 16 instructions. The AHB writes the instruction in the queues and then it gets freed. In case of any read instruction, the controller issues a burst instruction to the memory and the block of data is stored in the 4 queues. This provides a cache like behavior to the AHB. Thus the read actions is made faster by reducing the scheduler timing by issuing a burst instruction instead of a single read.
The complete operation of the memory controller can be described with Fig. 5, using the state machine. The command generator and command scheduler are described as under.
Command Generator.
Command generator generates the commands which serve the DDR without violating timing constraints.
Coming to the command priorities, the read and write commands have high priority, as they put data on the bus. Recharge and activate commands have lower priorities. The command generator works on the state machine shown in the Fig. 5, to take the decision for which command has to be generated for what condition.
There can occur three cases when a command is issued.
1. Row Empty 2. Row Conflict 3. Row Hit
When the row is empty, directly the required row is activated. For a row conflict, the row in the row buffer is precharged first and then the required row is activated. If there is a row hit the required operation can be
performed directly. The working of this is indicated as a state machine in the figure.
Command Scheduler.
The command scheduler gives the timing analysis for all the commands which are generated from the command generator. A parameter T is defined for every operation to indicate the time required for each command. The timing details for DDR are taken from the standards listed in the data sheet.
Fig. 5. State Machine for Memory Controller Operation
IV. SIMULATION AND RESULTS
Fig. 6. Simulation result for DDR SDRAM
Fig. 7. Simulation result for Unmodified DDR Controller
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Fig. 8. Simulation result for Modified DDR Controller With a 4 queue implemenatation we can see the performance of the controller is increased by 60-65% , and 75-85% increase in case of 8 queue implementation.
V. CONCLUSION
A high speed DDR memory controller interfaced with AHB is proposed, verified and evaluated with various sequences of data transfers. A maximum of 93.3452%
reduction in the delay is observed with the queuing technique, resulting in the improvement in terms of performance. This can be extended to different families of DDR for further improvement.
REFERENCES
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[2] Ching- SDRAM Controller Applications”.IEEE J. Solid-State Circuits, Vol.39, Nov. 2004.Che Chung, Pao-Lung Chen, and Chen-Yi Lee.
[3] Micron Technology Inc., Synchronous DRAM Data Sheet, 2001.
[4] ARM, AMBA Specification Rev.2.0, 1999.
[5] “Memory Controllers for Real-Time Embedded systems” Benny Akesson Kees Goossens vol. 3, no. 3, pp. 75–77, Mar1999.
[6] Hynix Semiconductor Inc., SDRAM Device operationRev.1.1, Sep. 2003.
[7] Samir Palnitkar, Pearson 2nd edition “Verilog HDL, A Guide to Digital Design and Synthesis.
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