AN ANALYSIS OF HYBRID MULTI-BIT ∑∆ ADC ... - IRD India

International Journal of Recent Advances in Engineering & Technology (IJRAET)

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AN ANALYSIS OF HYBRID MULTI-BIT ∑∆ ADC ARCHITECTURES

B. SekharaBabu, Dr. Sumithra Devi K.A.

Research Center, Dept. of ECE, R.V.C.E, Director, M.C.A. Dept, R.V. College of Engineering Bangalore, Karnataka, India,

Email : digitalshekar@gmail.com, sumithraka@gmail.com

Abstract:--The scaling of CMOS technologies has increased the performance of general purpose processors and DSPs while analog circuits designed in the same process have not been able to utilize the process scaling to the same extent, suffering from reduced voltage headroom and reduced analog gain. In order to design efficient analog‐to‐digital converters in nanoscale CMOS there is a need to both understand the physical limitations as well as to develop new architectures and circuits that take full advantage of what the process has to offer.

Sigma Delta ADCs are promising candidates for A/D conversion in modern wireless transceivers. Multi-bit sigma-delta modulators are widely used in analog-to-digital conversion especially in the modern deep-submicron CMOS process. They are naturally suitable for high- resolution narrow-band A/D conversions.

This paper studies an in-depth understanding of the performance of state-of-the-art hybrid ∑ΔMs. With this objective in mind this paper gives an overview of reported cutting-edge hybrid ∑ΔM ADCs fabricated in CMOS technologies. The data used for this study was mainly collected from the IEEE Journal of Solid-State Circuits as well as the major conferences sponsored by the IEEE Solid-State Circuits Society (SSCS), namely International Solid-State Circuits Conference (ISSCC), European Solid- State Circuits Conference (ESSCIRC), Custom Integrated Circuits Conference (CICC), Symposium on VLSI Circuits (VLSI), Asian Solid-State Circuits Conference

The goal of this work is to present an architecture study of Delta-Sigma AD Converters and to provide insight into a wide range of analog circuit imperfections which can limit the performance.

Keywords: ∑Δ ADC, CMOS, DSPs, IEEE, VLSI.

I. INTRODUCTION

ALTHOUGH ∑Δ modulators were first introduced as continuous-time (CT) circuits [1], with the advent of

switched-capacitor (SC) MOS circuits discrete-time (DT) circuits were adopted for most implementations of such modulators. However, because of unity-gain frequency requirements on the amplifiers in SC integrators, it has been difficult to extend the signal bandwidth of DT ∑Δ implementations of modulators beyond a few megahertz while maintaining high resolution. Recent research has led to DT ∑Δ modulators with nearly 4 MHz bandwidth but with resolutions of 9 bits or less [2], [3]. The largest signal bandwidth reported recently for a DT modulator is 5 MHz, but with only 7 bits of resolution [4]. Recent CT modulators have achieved bandwidths of 10 MHz in 0.18µm CMOS technology [5], [6] and 15 MHz [7] and 20 MHz [8] in 0.13µm CMOS technology, all with a resolution of 11 bits or more. These results suggest that CT implementations are capable of operating at signal bandwidths difficult to achieve with DT designs while still maintaining a high resolution.

This Paper studies the various architecture of Hybrid-

∑Δ ADCs. Section II describes the basics of ΣΔ adcs. In Section III, different hybrid architectures is reviewed, while Section IV presents the conclusion with table of different architectures.

II. BASICS OF ΣΔ ADCS

Contrary to the Nyquist ADCs, which are open loop systems from a control perspective, Sigma-Delta (ΣΔ) ADCs rely on a feedback path to achieve a closed-loop control of the quantization error. The fundamentals on how the shaping of quantization noise is implemented in practice, as well as the basic architecture, performance metrics, and ideal behavior of oversampling noise- shaping ADCs is presented below. Figure 1 illustrates the basic block diagram of a ΣΔ ADC intended for the conversion of LP signals, which consists of the

following:

Antialiasing filter (AAF), which band limits the analog input signal to avoid aliasing during its subsequent

sampling. Oversampling considerably relaxes the attenuation requirements of the AAF, so that smooth transition bands are usually sufficient compared to

nyquist-rate ADCs.

Fig. 1General block diagram of a ΣΔ ADC. A low-pass discrete-time ΣΔM is assumed

Sigma-Delta modulator (ΣΔM), in which the oversampling and quantization of the band-limited analog signal take place. The quantization noise of the embedded B-bit quantizer is shaped in the frequency domain by placing an appropriate loop filter H(z) before it and closing a negative feedback loop around them.

Low-resolution quantizers, with B typically in the range 1–5 bit, are sufficient for obtaining small in-band noise power (IBN) and high accuracy in the A/D conversion.

Decimation filter, in which a high-selectivity digital filter sharply removes the out-of-band spectral content of the ΣΔM output and thus most of the shaped quantization noise. The decimator also reduces the data rate from fs down to the Nyquist frequency, while increasing the word length from B to N bits to preserve resolution.

Fig. 2 ΣΔ modulator: (a) block diagram and (b) ideal linear model.

The ΣΔ modulator is the block that has most influence on the performance of the ADC, basically because it is responsible for the sampling and quantization processes that ultimately limit the accuracy of the A/D conversion.

A. Signal Processing in ΣΔMs

The basic scheme of a ΣΔ modulator consists of a loop filter H(z) and a B-bit quantizer in a feedback loop, as shown in Figure 2a [9]. Let us consider that the gain of the loop filter is large within the signal band and small outside it. Owing to the action of negative feedback, the analog input signal x and the analog version of the ΣΔM output y will practically coincide within the signal band, so that the error signal x − y in this closed loop system is very small within the signal band. As the B-bit quantizer is uniform, most of the differences between the input and the output of the ΣΔM will be placed at higher frequencies, so that the quantization noise is shaped in the frequency domain and most of its power is pushed outside the signal band.

Using the linear additive white noise model for the embedded quantizer, the ΣΔM in Figure 2a can be modeled as the two-input (x and e) one-output (y) linear system in Figure 2b, which is described in the Z-domain as

( ) ( ) ( ) ( ) ( )

Y z  STF z X z  NTF z E z

(1) where STF and NTF stand for the signal and noise transfer functions, respectively given by

( ) 1

( ) , ( )

1 ( ) 1 ( )

q

q q

k H z

STF z NTF z

k H z k H z

 

  ⁽²⁾

Fig. 3 PDM output signal of a first-order, ΣΔ modulator with an embedded 3-bit quantizer for an input sinusoid.

Note that, if the loop filter is designed such that |H(f )| >

1 within the signal band, then |STF(f )| ≈ 1 and |NTF(f )|

< 1; that is, the quantization noise is ideally canceled while the input signal is perfectly transferred to the output. For the conversion of LP signals, the simplest loop filter H(z) that exhibits the desired frequency performance is an integrator,

1

( )

1

1 ITF z z

z









⁽³⁾

that, in combination with an embedded quantizer with k_q= 1, leads to a ΣΔM whose output is given by

1 1

( ) ( ) (1 ) ( )

Y z  z X z

^

  z

^

E z

⁽⁴⁾

and builds up a first-order, high-pass shaping of the quantization noise. For the sake of illustration, Figure 3 shows the output signal of a first-order ΣΔM with an embedded 3-bit (8-level) quantizer for a sinusoidal input signal. Note that, due to the combined action of oversampling and negative feedback, the modulator output is a pulse density modulated (PDM) signal whose local average tracks the input signal value within adjacent code transitions.

B. Performance Metrics of ΣΔMs

Contrary to Nyquist-rate ADCs, whose performance is mainly characterized by static performance metrics, that is, monotonicity, gain and offset errors, differential nonlinearity (DNL), and integral nonlinearity (INL) [10], ΣΔ ADCs’ characteristics are typically measured using dynamic performance metrics, which are obtained from the frequency domain representation of the time- domain digital output sequence. The latter thus requires the computation of the fast Fourier transform (FFT) of a finite-length output sequence with a specific windowing function.

Noise and power metrics are derived from the ΣΔM output spectra by integration over the signal bandwidth and are typically collected in a single plot as shown in Figure 4. These metrics are usually the most important measures and comprise the following:

Fig. 4 Illustration of the performance metrics of a ΣΔ modulator on a typical SNR curve.

Signal-to-noise ratio (SNR), which is the ratio of the output power at the frequency of an input sinusoid to the

uncorrelated IBN:

,

( ) 10log

10

P

^{sig out}

SNR dB

IBN

 

  

 

⁽⁵⁾

It accounts for the modulator linear performance only, so that the in-band power associated to harmonics of the input signal is not considered as part of the IBN for SNR computation. If an ideal ΣΔM is considered and only the in-band quantization noise is accounted for in the IBN computation, the term signal-to-quantization-noise ratio (SQNR) is often employed.

Signal-to-noise-plus-distortion ratio (SNDR), which is defined as the ratio of the output power at the frequency of an input sinusoid to the total IBN power, also accounting for possible harmonics at the ΣΔM output.

As illustrated in Figure 4, this makes a typical SNDR curve to deviate from the SNR curve only for large input amplitudes, for which the generated distortion is noticeable. Therefore, the output spectra from which the SNDR curve is computed are typically obtained by applying an input signal at f_in≤ Bw/3 (for LP ΣΔMs), so that at least the second and third harmonics lie within the signal band.

Dynamic range (DR), which can be defined as the ratio of the output power at the frequency of an input sinusoid with maximum amplitude to the output power for a small input amplitude for which SNR = 0 dB; that is, so it cannot be distinguished from the error. Ideally, a sinusoid with maximum amplitude at the modulator input will provide an output sinusoid sweeping the full- scale range YFS of the embedded quantizer, so that

2 , ,max

10 10

( / 2)

( ) 10log 10log

2

sig out FS

P Y

DR dB

IBN IBN

 

 

    

    ⁽⁶⁾

Effective number of bits (ENOB): as the DR of an ideal N-bit Nyquist-rate converter is given by Equation 6 with OSR = 1, a similar expression can be established for ΣΔMs

( ) 1.76 ( )

6.02 DR dB

ENOB bit 



(7)

( ) 6.02 1.76 10log (

10

)

DR dB  N   OSR

where ENOB can be defined as the number of bits needed for an ideal Nyquist-rate ADC to achieve the same DR as the ΣΔ ADC. The performance of oversampled ΣΔ converters and Nyquist-rate ADCs can thus be compared in a simple way [11]. Instead of the DR, the peak SNDR is also often used in equation 7 to express the accuracy of the A/D in a ΣΔmodulator in bits.

Overload Level (OL): as illustrated in Figure 4, the SNR of a ΣΔ modulator increases monotonously with the input signal amplitude (A_in), but sharply drops for input amplitudes close to half of the full-scale input range of

the embedded quantizer (X_FS/2)due to its overload and the associated IBN increase. The overload level is considered to define the maximum input amplitude for which the ΣΔM still operates correctly and can almost be arbitrarily defined, but it is typically chosen as the amplitude for which the SNR drops 6 dB below the peak SNR [12].

III. HYBRID∑ΔM ARCHITECTURES

Some of the most relevant cutting edge ∑ΔM topologies that are in the frontiers of the ∑ΔM designs are:

 SturdyMASH(SMASH)architectures

 Hybrid∑ΔMarchitectures,including∑ΔM- NyquistADCs,active–passiveCT-

∑ΔMs,CT/DTcircuitimplementations

 Multirate∑ΔMs

 Multibit∑ΔMswithtime-codedquantization

 ∑ΔMsimplementedwithdigital- basedcircuittechniques

 Adaptive/reconfigurable∑ΔMs

 Ultra-high-speed∑ΔMsforRFdigitization.

An interesting approach in the design of high- performance ∑ΔM s consists of using hybrid circuit and /or architecture techniques to improve the efficiency of the digitization as compared to conventional ∑ΔMs. The term hybridis used here to denote those kinds of ∑ΔMs that are not, strictly speaking, and pure ∑ΔMs.

Fig. 5 Example of the first reported hybrid ∑∆M-Pipeline ADCs [18].

A. Hybrid∑ΔMs-NyquistADCs

A first category of H-∑ΔM architectures is that which results from combining a Nyquist rate ADC usually apipeline, SAR, orcyclic ADC anda ∑ΔM[13, 14, 15, 16, 17, 18]. In the majority of cases, the basic strategy follow edinthis kind of H-∑ΔMs consists of replacing the embedded multibit flash ADC with another kind of Nyquist-rate ADC architecture, namely pipeline [17, 18], two-step[16], SAR[13], or

Cyclic [14, 16]. Essentially, the main advantage o f this strategy is to provide a wa y o f i n c r e a s i n g the number of levels of the internal Quantizer without the prohibitive exponential growth of the power consumption and silicon are aofflash ADCs.

The idea of hybrid ∑ΔM-Nyquist ADCs has been implemented in both single-loop and cascade architectures, featuring competitive performance in different applications cenarios. Asanillustration, Figure5 shows the conceptual block diagram of one o f the f i r s t reported hybrid ∑ΔM-Nyquist ICs, which consists of i n a c a sc ade o f a5 - bit second order ∑ΔM and a

12-bit fourth-stagepipelineADC[18].

Oneofthemaininconveniencesofcombining∑ΔMsandNyq uist-rateADCsisthatasthenumberofbitsoftheNyquist- ratesubADCincreases;thecircuitcomplexity,sensitivitytoc ircuiterrors,andlatencyincreasesaswell,withtheriskoflosin gthebenefitsprovidedby∑ΔMsintermsofsystemsimplicity

androbustnessagainstcircuitnonidealities.Therefore,altho ughverycompetitiveperformancecanbeachievedbyreplaci ngmultibitflashADCswithotheralternativeNyquist- rateADCs,thementioneddesigntrade-

offshavemotivated∑ΔMdesignerstoexplorealternativeim plementationsto conventionalmultibitquantization.

Fig. 6 Example of the hybrid active/passive ∑∆M reported in [19]

B. Hybrid Active/Passive ∑ΔMs

Another kind of H-∑ΔMs corresponds to a family of CT-∑ΔMs in which the loop filter is implemented by hybrid active/passive circuit elements. Thus, part of the loop-filter integrators are implemented as passive-RC networks, while others are implemented as active-RC or Gm-C circuits. The motivation for using this approach is to reduce the number of OTAs and hence reduce the power dissipation, as OTAs are the circuit blocks that consume most of the power in a ∑ΔM. The design issues associated with loop-filter OTAs aggravate in nanometer CMOS technologies with reduced supply voltage, and particularly in wideband applications where the dynamic requirements of the operational amplifiers yield in many cases to very power-hungry circuit solutions.

In this scenario, replacing some active integrators with passive-RC networks in the ∑ΔM loop-filter results in a more efficient solution. Apart from the power saving, integrated passive-RC networks have better linearity than their active counterparts. However, the main limitation of using passive integrators is that they do not provide any gain that makes the loop filter more sensitive to their error mechanisms. This limitation can be partially palliated if the active integrators are used at the front-end of the modulator, so that the effect of thermal noise of the passive-RC networks and other circuit nonideal

effects can be reduced by the preceding active integrators. Figure 6 shows an example proposed by Song et al. in [19].

The modulator architecture consisting of a fifth-order single-loop architecture uses five integrators, two of them implemented by passive-RC networks. These passive integrators are placed in the second and fourth positions of the modulator chain, so that their nonideal effects can be attenuated by the gain of active integrators.

A good example is the fourth-order BP-∑ΔM reported by Chaeet al. [20], which digitizes 24-MHz band-pass signals located at 200 MHz with 58-dB SNDR while consuming 12 mW. This circuit is implemented by using single-opamp high-Q resonators that incorporate positive feedback to achieve high Q and are implemented by combining an active LPF and a passive HPF. Another interesting example was proposed by Srinivasan et al. [21], who reported a third-order CT-∑ΔM made up of a front-end passive- RC integrator followed by two Gm-C integrators. The chip fabricated in a 45-nm CMOS technology digitizes 60MHz signals with 61-dB SNDR and 20 mW power consumption, while clocked at 6 GHz one of the highest clock frequencies reported by ∑ΔM ICs to date.

Fig. 7Example of the hybrid CT/DT cascade ∑∆Ms reported in [22]

Fig. 8 Conceptual block diagram of a conventional (upscaling) cascade MR-∑∆M: (a) DT scheme and (b) hybrid CT/DT scheme.

C. Hybrid CT/DT ∑ΔMs

The third category of H-∑ΔMs corresponds to those

∑ΔMs in which the loop filter is implemented by both SC and CT integrators, thus taking advantage of both circuit techniques. CT-∑ΔMs operate at faster rates than their SC counterparts with relatively lower power dissipation. However, CT-∑ΔMs are more sensitive than SC-∑ΔMs to some circuit and architecture

error mechanisms, such as circuit element tolerances, excess loop delay, and clock jitter error. Some authors have tried to circumvent the mentioned limitations of CT-∑ΔMs by using the so called hybrid CT/DT ∑ΔMs, in which some parts of the loop filter usually the front- end building blocks are implemented using CT circuits, thus providing potentially faster operation and embedded antialiasing filtering with reduced power consumption [22, 23, 24, 25, 26, 27, 28]. Thus, hybrid

CT/DT ∑ΔMs have been demonstrated using both single-loop [23, 25] and cascade ICs [22]. The most common situation in practice consists of using a CT front-end integrator, whereas the remaining integrators in the modulator loop are implemented using SC circuit techniques.

As an illustration, Figure 7 shows one of the first practical implementations of a hybrid CT/DT cascade

∑ΔM, proposed in [22]. This modulator is a cascade of a second-order (active-RC) CT∑ΔM stage with a first- order SC stage, considering 4-bit quantization in both stages. In spite of the mentioned advantages, reported hybrid CT/DT -∑ΔM ICs do not really exploit the potential capability of CT circuits integrated in CMOS processes to operate up to the gigahertz range with reasonable linearity. This is partially due to the fact that the maximum sampling rate of hybrid CT/DT-∑ΔMs is indeed limited by the SC part of the modulator loop filter. A possible solution to alleviate this restriction could be usingthe so-called multirating.

D. Hybrid CT/DT Cascade MR--∑ΔMs

The concept of MR--∑ΔMs can be extended to hybrid CT/DT implementations as conceptually depicted in Figure 8b, that represents a cascade two-stage MR H--

∑ΔM. The circuit nature (either CT or DT) of the different modulator blocks as well as their corresponding sampling frequencies are highlighted.

The use of a complete CT stage (instead of just the front-end integrator for instance) maximizes the embedded AAF, while taking advantage of the relaxed dynamic requirements of the front-end CT circuits as compared to their DT counterparts [22]. The concept of MR--∑ΔMs can be extended to hybrid CT/DT implementations as conceptually depicted in Figure 8b, that represents a cascade two-stage MR H--∑ΔM. The circuit nature (either CT or DT) of the different modulator blocks as well as their corresponding sampling frequencies are highlighted. The use of a complete CT stage (instead of just the front-end integrator for instance) maximizes the embedded AAF, while taking advantage of the relaxed dynamic requirements of the front-end CT circuits as compared to their DT counterparts [22].

The analysis of Figure 8b can be carried out by applying a DT – CT transformation to the front-end stage of Figure 8b. The resulting MR H--∑ΔM is equivalent to the original MR DT--∑ΔM.

E. Downsampling Hybrid CT/DT Cascade MR--

∑ΔMs

Using lower values of the OSR in the front-end CT stage of Figure 8b may be beneficial when the subsequent SC stages can operate at high enough values of OSR.

However, the use of high values of OSR in the back-end stages is not practical when digitizing wideband signals, for instance in the order of 10 – 100 MHz. In these cases, sampling rates in the order of gigahertz may be necessary to digitize such signals with low-medium effective resolutions (8 – 10 bit). Therefore, the use of back-end SC stages may be not feasible because of the prohibitive values of GB required for the operational amplifiers.

The mentioned problems can be alleviated if the concept of multirating is redefined just in the opposite way as it was conceived, that is, going from an upsamplingMR system in which the front-end stage rate is increased in the subsequent stages to a downsamplingMR system in which the front-end (CT) stage operates at the highest rate, thus benefiting from their potentially faster operation [29].

Figure 9 shows a conceptual block diagram of a downsampling(two-stage) cascade MR H--∑ΔM architecture proposed in [29]. In contrast to conventional (upsampling) MR H--∑ΔMs, the back-end (DT) stage operates at a rate lower than that of the front-end (CT) stage, that is, f_s2 < f_s1. The main drawback of this approach is the aliasing caused by the downsampling processing, which requires using an interstage AAF.

However, as shown in [29], the operation of the AAF can be completely translated to digital domainby using two additional digital blocks of the transfer functions which are named H₁(z) and H₂(z). In this way, Figure 5.24 has the same number of analog building blocks as a conventional cascade -∑ΔM.

Therefore, the operation behind the modulator in Figure 9 is essentially the same as in conventional cascade -

∑ΔMs. The main difference is that the DCL transfer functions are designed so that they must remove not only the quantization error of the front-end stage E₁(z), but also its aliased components. To this purpose, H₁(z) and H₂(z) must bereconfigurable and programmable according to the value of the downsampling ratio (p

≡fs1/f_s2 > 1). These functions are completely implemented in the digital domain, withoutany extra analog hardware required, and can be easily synthesized for different

values of p as detailed in [29]. As a consequence, the resulting MR--∑ΔMs are potentially faster, less sensitive to circuit error mechanisms, and more power efficient than conventional upsampling MR architectures.

Fig.9 Conceptual block diagram of a downsampling cascade hybrid CT/DT MR-∑∆M [29]

Table1 State-of-the-arthybrid∑∆Ms

Ref. DR (bit) Bw

(Hz)

OSR HybridTechni que

Tech./supply voltage(V)

Power(W) FOM (pJ/conv) [30] 16.7 2.42E+04 135 CT-DT 40nm/1 5.00E−04 0.10 [31] 13.8 5.00E+06 8 ∑∆M-pipeline 0.18m/1.8 2.20E−02 0.15 [32] 13.0 5.00E+06 9 Active–passive 55nm/1.3 1.30E−02 0.16 [15] 12.2 5.00E+06 16 ∑∆M-cyclic 0.18m/1.8 7.90E−03 0.16 [16] 12.2 1.56E+06 8 ∑∆M/two-step 0.18m/1.2 2.60E−03 0.18 [33] 11.2 1.20E+06 15000 Active–passive 65nm/1.4 1.16E−03 0.21 [19] 10.9 2.00E+06 38 Active–passive 0.28m/1.5 2.70E−03 0.35 [34] 12.5 2.00E+05 375 Digital-based 65nm/1.3 9.50E−04 0.41 [14] 11.7 1.00E+07 5 ∑∆M-cyclic 0.18m/2 4.80E−02 0.72 [37] 10.0 1.92E+06 48 ∑∆M-SAR 130 nm/1.2 3.10E−03 0.79 [35] 8.9 5.00E+06 8 Digital-based 0.18m/1.8 4.00E−03 0.85 [36] 11.0 3.13E+06 16 CT-DT 65nm/1.1 1.10E−02 0.86 [22] 12.5 7.50E+06 16 CT-DT 0.18m/1.2 8.90E−02 1.02 [35] 12.4 2.00E+05 16 Digital-based 0.18m/1.8 4.00E−03 1.89 [17] 12.2 1.00E+07 4 ∑∆M-pipeline 0.18m/3.3 2.40E−01 2.55 [23] 15.9 4.80E+04 128 CT-DT 0.35m/3.3 1.80E−02 3.07 [24] 16.5 2.00E+04 256 CT-DT 65nm/3.3 1.50E−02 4.10 [25] 16.7 2.00E+04 128 CT-DT 0.18m/3.3 3.73E−02 8.76 [38] 9.5 4.00E+06 500 Active–passive 90nm/1.2 5.40E−02 9.32 [39] 13.0 1.10E+04 64 CT-DT 0.5m/1.8 1.70E−03 9.43 [18] 14.5 1.25E+06 8 ∑∆M-pipeline 0.6m/5 5.50E−01 9.49

IV. CONCLUSION

This paper presents the state of the art on CMOS hybrid ∑∆Ms, making a systematic classification of their architectures. The paper is concluded with a review of cutting-edge ∑∆M ICs, considering diverse circuits and systems techniques, namely: advanced cascade topologies, hybrid implementations and MR architectures, etc. It could be said that compared to other kinds of ADCs, ∑∆M techniques cover the widest resolution-versus-bandwidth region, targeting more and more applications and taking advantage of CMOS technology downscaling. This trend is expected to continue with the development and improvement of some architecture and circuit techniques. Table 1 shows the different state of art ∑∆m adcs w.r.t DR, OSR, hybrid technique, technology, supply voltage, power and figure of merit.

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