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Abstract
Jitter defines the deviation of data/clock transition from its ideal position and it is one of the most important performance metrics in high-speed system design. The rapid growth of bandwidth requirement in high-speed wire-line data path communications like I/O interfaces, memory and graphic interfaces, near-term architectures, serial I/O systems, etc., pushes the data rate to higher and higher in recent years. At such a high data rate, the parasitic effects in the high-speed components like drives, clock buffers, I/O interfaces, phase-locked loops (PLLs), and clock data recovery systems (CDRs) induce jitter. Again the skin effect and dielectric loss in the transmission mediums like copper cables, printed circuit board (PCB) traces, and backplanes cause significant distortion of high-frequency signals, leading to considerable inter symbol interference (ISI) on the output data which again creates jitter. Furthermore, power supply noise, oscillator’s phase noise, and process, voltage, and temperature (PVT) variation increase jitter in the data or clock signals. As jitter in the data streams or clock signals degrades the performance of high-speed systems, it is essential to measure the jitter contributed by high-speed drivers, clock buffers, I/O interfaces, phase-locked loops (PLL), and other critical blocks to evaluate different performance metrics. Also, the jitter information helps designers to enhance the performance of the high-speed system by doing some careful circuit design, implementing some jitter reduction techniques, or developing some feedback control mechanism for jitter reduction.
Jitter measurement can be done by off-chip or on-chip. Since the jitter, related to the timing is very small in absolute magnitude but proportionally large compared to high- speed data/clock periods. Accurate measurements of such timing jitters are very difficult in the off-chip method. Again off-chip jitter measurement requires high power consumption, large area and dedicated output drivers, high-speed I/O circuits and pins, high-frequency probe and probe stations, and costly equipment. Due to these limitations in the off-chip jitter measurement, the on-chip jitter measurement (OCJM) technique is highly appreciated because of its accurate jitter measurement and low-cost solution. The most important advantage of the OCJM technique is, it can monitor the jitter and optimize the circuit performances by controlling and calibrating critical parameters inside the chip.
This thesis presents three contributions in the area of on-chip jitter measurement, which can be used to help optimize the performance of high-speed wire-line transceivers.
In this regard, a novel transition region scanning based on-chip jitter measurement circuit is developed along with an automatic error detection/correction mechanism. Additionally, an on-chip jitter generation circuit is developed which is used to characterize and validate the OCJM circuit.
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In the first work, an on-chip jitter measurement circuit is developed using a novel transition region scanning technique that measures peak-to-peak jitter for a 10 Gb/s SerDes system. This technique first converts the peak-to-peak transition region width of data/clock to equivalent pulse width and subsequently, the pulse width is scanned by a slowly moving clock edge to construct peak-to-peak jitter width. The peak-to-peak jitter width finally converts to an equivalent peak voltage and is measured at the output of the chip which gives the on-chip jitter information in the form of voltage. To accomplish the proposed jitter measurement method, a pulse width generator, a transition region scanner, a phase shifter, and, a jitter-to-voltage converter circuit is developed. The pulse width generator generates a pulse and the pulse width scanner scans the pulse width with the help of a phase shifter. The jitter-to-voltage converter contains a time-to-voltage converter (TVC) circuit which is used to convert timing jitter to voltage and a peak voltage detector (PVD) circuit which is responsible for giving the peak voltage corresponding to the peak-to-peak jitter.
In the second work, an automatic error detection and correction circuit is developed which prevents both static and dynamic errors in the course of jitter measurement. It also helps to reduce the measurement error due to process, voltage, and temperature variations. The technique calibrates the cursors (clock edge) position for error-free scanning of the whole pulse width. To accomplish this task a start-to-end circuit, a cursor detection circuit, a cursor correction circuit, and a control voltage generation circuit are developed. The start-to-end circuit gives the information of starting and ending timing of the jitter. Based on starting and ending timing information, the cursor detection circuit detects the cursor position and the cursor correction circuit generates an appropriate signal and sends it to the control voltage generator. The control voltage generator receives the appropriate signal from the cursor correction circuit and generates the control voltage which helps to reposition the cursor.
Finally, an on-chip jitter generation unit is developed for the characterization and validation of the proposed on-chip jitter measurement circuit. For this work, a data generation circuit, a clock generation circuit, and a jitter generation circuit are implemented. The data generation circuit is a high-speed serializer that generates 10 Gb/s serialized data, the clock generation circuit is a PLL which generates a 10 GHz clock, and the jitter generation circuit takes either serialized data or clock signal and produced a jittery data or clock signal by the help of a low frequency and low amplitude sinusoidal control voltage. A test chip has been designed and fabricated using 65 nm CMOS technology with a core silicon area of 910 µm × 300 µm. The complete architecture consumes 11.4-mW at a 10-Gb/s data rate. The measurement result confirms that the output peak voltage varies proportionally with the peak-to-peak jitter of target jittery data or clock signal. The jitter resolution and dynamic range are estimated in sub-picosecond and 0.8 UI respectively.
