Therefore, storing and then generating test patterns obtained by ATPG algorithms on the SUT (discussed in Module XI) using the hardware test pattern generator is not feasible. Instead, the test pattern generator is basically a type of register that generates random patterns that act as test patterns. The main emphasis of the register design is to have a low area, yet generate as many different patterns as possible (from 0 to 2n-1, if there are n flip-flops in the register).
Output Response Compactor: The Output Response Compactor performs lossy compression of the CUT outputs. The output of the CUT must be compared to the expected response (called the golden signature. Similar to the case of the test pattern generator, the expected output responses cannot be explicitly stored in memory and compared to the CUT responses.
Thus, the CUT response must be compressed in such a way that comparisons with expected responses (golden signatures) become easier in terms of the area of memory that stores the gold signatures. The value of hi i n 1), indicates that the output of flip-flop Xi provides feedback to the linear XOR function.
Standard LFSR: Example
It can be noted that this LFSR generates all the patterns (except all 0's) generated by a 3 bit counter, but the area of the LFSR is much lower compared to a counter. In a real scenario, the number of inputs of a CUT is of the order of hundreds.
Module-XI Lecture-II
Built in Self Test
Modular LFSRs
In modular LSFR, the output of a flip-flop may or may not participate in the XOR function; if the output of any flip-flop Xi, for example, provides input to the XOR gate from output of flip-flop Xi to input of flip-flop Xi1; otherwise, the output of flip-flop Xi is fed directly to the input of flip-flop Xi1.
Modular LFSRs: Example
Only for a few characteristic polynomials is the LFSR of maximum length; such polynomials are called primitive polynomials (a list of such polynomials is available in Bardell et al.
Hardware response compactor
Number of 1s compaction
It should be noted that the LFSR generated 7 samples (unsimilar) which when given as input to CUT produce an output as 0001000 which makes the number of 1s equal to 1. So the error can be detected by compression as there is a difference in the number 1 s at the CUT output for the given input samples. It should be noted that according to the input patterns, a value of 1 is stored (as a golden signature) in memory, which is compared to the compressed CUT response.
So error cannot be detected by the compaction; the number of 1s at the output of the SUT for the given input patterns is the same under normal and s-a-1 conditions. In other words, for the input patterns (of the LFSR), "number of 1's" based compression is aliasing.
Transition count response compaction
Questions and Answers
If the seeds are all in the 0 state, the LFSR will be stuck in the 0 state because the feedback logic is XOR gates.
Module-XI Lecture-III
Memory Testing
Introduction
During the production test, it is not only necessary to detect defects, but also to diagnose their locations (in terms of number of cells). Since almost all memories have errors in some cells, there are redundant (redundant) cells in the memory. When a fault is diagnosed, the corresponding cell is disconnected and a new fault-free cell is connected in its place.
The only functionality of a cell is to store a bit of information which is implemented using a capacitor; when the capacitor is charged it represents 1 and when there is no charge it represents 0. Using logic gates (in flip-flops) instead of capacitors to store the bit information would lead to a very large area. In this lecture we will study the most commonly used error patterns and testing techniques for such memory error patterns.
Memory fault models
When data needs to be read from memory, the row and column decoders first determine the location (i.e. the cell) based on the address (sent in the address bus) to be accessed. Based on the address in the row and column decoders, the cell of the relevant row and column is connected to the sense amplifier, which transmits the data. A similar situation (for access to the required cells) applies when data needs to be written into memory. However, in the case of writing, special control circuits write the values in the cells from the data bus.
The row and column decoders are digital circuits implemented using logic gates (which differ from the memory cell implementation). When testing the memory, we do not consider the decoders as gate-level digital circuits, nor the sense amplifier and driver as analog circuits. We test the functionality of the decoders to see whether they can access the desired cells based on the address in the address bus.
For the amplifier and driver we check that they can correctly pass values to and from the cells.
Stuck-at fault
Transition fault
Coupling Faults
Inversion coupling faults
The loop itself in state S00, denoted w0@i means that if 0 is written in cell i, then the same state is preserved; another transition w0@j is associated with the same loop itself, which means that if 0 is written to cell j, then S00 is stored. Under normal conditions if we write 1 in cell j (from stateS00) we go to stateS01, however, in increasing cfinvi j, we go to stateS11.
Idempotent coupling faults
We note that under normal conditions if we write 1 in cell j (from state S00) we go to state S01, however, on increment-1 cfidi j, we go to state S11. However, unlike the inverse coupling error, in the incremental-1 idempotent coupling error we do not have a false transition from S10 to S01.
Bridging fault
OR bridging fault ORbfi j, (involving cells i and j ) which results in values in cells i and j to be logic OR of the values in these cells under normal condition.
Neighborhood pattern sensitive coupling faults
The black cell is the one under test, and the four cells around it (filled with small check boxes) are called neighborhood cells. The value in the cell under test changes due to a change in ONE neighboring cell (type-1 or type-2 depending on which one is used); all other neighborhood cells make a pattern. PNPSF implies that a certain neighborhood pattern prevents the cell under test from changing its value.
Address decoder faults
Testing of memory faults
March Test: Stuck at fault model
March Test: Transition fault
Module-XI Lecture-IV
March Test: Coupling Faults
It may be noted that first cell k is written with 1; as cell i is coupled with cell k having fault | , the 0 to 1 transition in cell k inverts the content of cell i. Following that, cell j is written with 1; as cell i is also coupled with cell j having fault | , the 0 to 1 transition in cell j inverts the content of cell i again. Now when cell i is read, the value determined is 0 which means absence of two coupling faults (i) rising cfinvi j, and (ii) rising cfinvi k,.
Reverse rising coupling error | between cell i (linked cell) and j (linked cell): (i) Cell j must be written with a 0 and read back, (ii) value at cell i must be read and remembered, (iii) cell j is to be a 1 to be written and read back, and (iv) value at cell i must be read and checked to be the same as the one being remembered (i.e. no inversion has occurred). Reverse descending coupling error | between cell i and j: (i) Cell j must be written with a 1 and read back, (ii) value at cell i must be read and remembered, (iii) cell j must be written with a 0 and read back , and (iv) value at cell i must be read and checked to be the same as the one being remembered (i.e., no inversion has occurred). Idempotent Rising-0 coupling error | 0 between cell i and j: (i) Cell j must be written with a 0 and read back, (ii) cell i must be written with a 1 and read back, (iii) cell j must be written with a 1 and is read back, and (iv) value at cell i must be read and checked to be 1.
Idempotent Rising-1 link error |1 between cell i and j: (i) Cell j must be written with a 0 and read back, (ii) cell i must be written with a 0 and read back, (iii) cell j must be written with a 1 and read back, and (iv) value at cell i must be read and checked to be 0. Idempotent Falling-0 coupling error | 0 between cell i and j : (i) Cell j must be written with a 1 and read back, (ii) cell i must be written with a 1 and read back, (iii) cell j must be written with a 0 and read back, and (iv) value at cell i must be read and checked to be 1. Idempotent Falling-1 coupling error |1 between cell i and j : (i) Cell j must be written with a 1 and read back, (ii) cell i must be written with a 0 and read back, (iii) cell j must be written with a 0 and read back, and (iv) value at cell i must be read and checked to be 0.
March Test: Bridging faults
AND bridging error ANDbfi j, (involving cells i and j):. i) write 0 in cell i and 0 in cell j and read back the values (which must remain the same), (ii) write 0 in cell i and 1 in cell j and read back the values,. iii) write 1 in cell i and 0 in cell j and read back the values, and (iv) write 1 in cell i and 1 in cell j and read back the values. It can be noted that the above four test pattern sequence is enough to test OR bridging error, also because we write and read back all possible combinations in the two cells (involved in error) to see if they keep their values.
March Test: Address decoder faults
Basics of memory BIST
X MSB X
X LSB
