International Journal of Recent Advances in Engineering & Technology (IJRAET)
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An Efficient Implementation of 4X4 Vedic Multiplier using Power Gating Method
1Pathan Johnkhan, 2B. Nageswara Rao Naik
1PG Student (M.Tech), Dept. Of ECE, KKR & KSR Institute of Technology & Sciences, Guntur
2Assistant Professor,Dept. Of ECE, KKR & KSR Institute of Technology & Sciences, Guntur
Abstract—This paper proposed a vedic multiplier implemented using MT CMOS logic style and clock gating with their comparative analysis on thebasis of power and delay. A variety of multipliers have been reported in the literature but power dissipation and area used by these multiplier circuitsare relatively large. This paper proposed a high performanceand power efficient 4x4 multiplier design based on Vedicmathematics using CMOS logic style.. In this paper, vedic multiplier using MTCMOS and power gating technique are compared taking power consumption as parameter by varying time. The designs are tested in 0.12 nmtechnology. Vedic Multiplier is implemented in DSCH2 tool and synthesised in microwind tool
Keywords—Multi-Threshold Voltage CMOS (MTCMOS), Vedic multiplier, Power analysis.
I. INTRODUCTION
Building low-power VLSI system has emerged as significant performance goal because of the fast technology in mobile communication and computation.
The advances in battery technology are not commensurate with the advances in electronic devices.
So the designers are faced with more constraint; high speed, high throughput and at the same time, consumption of power as minimal as possible. The levels, such as the architectural, circuit, layout, and the process technology level. At the circuit design level, the possibility for power savings exists by means of proper choice of a logic style for implementing combinational circuits. In the absence of low-power design techniques such applications generally suffer from very short battery life, while packaging and cooling them would be very difficult and this is leading to an unavoidable increase in the cost of the product. Historically, VLSI designers have used speed as the performance metric.
High gains, in terms of performance and silicon area, have been made for Digital circuits. In general, small area and high performance are two conflicting constraints. The power consumption for any given function in CMOS circuit must be reduced for either of the two different reasons: The most important reason is to reduce heat dissipation in order to allow a large density of functions to be incorporated on an IC chip.
Any amount of power consumption is worthwhile as
long as it doesn‘t degrade overall circuit performance [4]. The other reason is to save energy in battery operated instruments same as electronic watches where average power is in microwatts
Power dissipation can be reduced by scaling the supply voltage. The scaling of supply voltage linearly with feature size was started from half-micron technology.
But the power supply scaling affects the speed of the circuit the need of the time is to put efforts in designing low-power and high speed circuits. MTCMOS technology has emerged as a promising alternative to build logic gates operating at a high speed with relatively small power dissipation as compared to traditional CMOS. MTCMOS is an effective circuit- level technique that provides a high performance and low-power design by utilizing both low and high- threshold voltage transistors. This technology is used for reducing sub threshold currents in standby mode while maintaining circuit performance.
Vedic mathematics is a part of four Vedas (books ofwisdom). It is part of Sthapatya- Veda, which is anupaveda (supplement) of Atharva Veda. It encompasses theexplanation of numerous modern mathematical terms thatincludes arithmetic, geometry, trigonometry, quadraticequations, factorization and even calculus. The word―Vedic‖was coined from the word
―Veda‖ which means therepertoire of all knowledge.
Vedic mathematics is commonlybased on 16 Sutras (or aphorisms) dealing with different typesof mathematics like arithmetic, algebra, geometry etc.The essence of Vedic mathematics is the fact that it reducesthe otherwise ponderous calculations in conventional mathematics that slows down the calculation processconsiderably. This is because the Vedicformulas are predicated on the principles which are generally used my humans. This is a very enticing field and presents some efficient algorithms which can be applied to numerous branches of engineering such as computing, image processing and digital signal processing.
When the physical design of the MTCMOS circuits is done, it is vital to consider the large current flowing through the current stopping transistors in active mode and the electro-migration in the wires should be taken
into account. The channel width is also very important due to the large current. There is a trade-off between the local and global sleep devices. The bottleneck with local sleep devices is that there will be a large area overhead due to the fact that there will be a lot of extra transistors.
MTCMOS
The MTCMOS approach is easy on combinatorial circuits, but it can be tricky on sequential circuits.
Should the power supply be turned off, all data stored in the circuit will be irreversibly lost. This is the main problem with MTCMOS circuits. To deal with this problem complex timing scheme must be used or extra circuits have to be added. Because of these added items the performance of the circuit would be degraded.
This will also require a larger die area and impose higher power losses. MTCMOS (multithreshold CMOS) reduces leakage current during standby mode and attains high speed in active mode.
In this technique high threshold voltage transistor are used to isolate the low threshold voltage transistor from supply and ground during standby mode. However by including extra transistor, MTCMOS circuit faces performance penalty compared to CMOS circuits, if the transistor are not sized properly. The high threshold voltage transistor are turned off during standby (sleep mode) , this result very low sub threshold passes from Vcc to ground. MTCMOS includes high Vt transistor to gate power and ground of a low Vt logic blocks as shown in figure 1.when the high Vt transistor are off resulting in a very low sub threshold leakage current.
When the high Vt transistor are turned on, low Vt are connected to virtual ground and Vdd.
Figure 1Power gating structure
Figure 2 Schematic diagram of Existing XNOR Gate
However there are three drawbacks in MTCMOS sequential circuits that is need to be eliminated: first is sequential circuit will lose data when sleep transistor are turned off, second is timing is critical for sleep signal and third is sizing of sleep transistor is very difficult task.
The existing design of XNOR gate is shown in Fig.2. It consists of 3 transistors as one pMOS and two nMOS.
When ab=00, nMOS (both) are OFF and pMOS is ON due to high gate voltage than threshold. As pMOS is strong ‗1‘ device it will pass complete logic ―high‖
signal at the output. When ab=01, one nMOS is OFF and other nMOS is ON. As nMOS is strong ‗0‘ device it will pass complete logic ―low‖ signal at the output.
When ab =10, nMOS (second) and pMOS are ON. As mobility of nMOS is nearly three times greater than pMOS, hence it will drive the output ignoring the effect of ON pMOS transistors which results into zero output.
When ab=11, both the nMOS transistors are ON and only nMOS will be responsible for driving the output.
II. VEDIC MATHEMATICS
The proposed Vedic multiplier is based on the Vedic multiplication formulae (Sutras). These Sutras have been traditionally used for the multiplication of two numbers in the decimal number system. In this work, we apply the same ideas to the binary 6number system to make the proposed algorithm compatible with the digital hardware.
Urdhva Tiryakbhyam
The multiplier is based on an algorithm Urdhva Tiryakbhyam (Vertical & Crosswise) of ancient Indian Vedic Mathematics. Urdhva Tiryakbhyam Sutra is a general multiplication formula applicable to all cases of multiplication. It literally means ―Vertically and crosswise‖. It is based on a novel concept through which the generation of all partial products can be done with the concurrent addition of these partial products.
The parallelism in generation of partial products and their summation is obtained using Urdhava Triyakbhyam explained in fig.3. The algorithm can be generalized for n x n bit number. Since the partial products and their sums are calculated in parallel, the multiplier is independent of the clock frequency of the processor. Thus the multiplier will require the same amount of time to calculate the product and hence is independent of the clock frequency.
The net advantage is that it reduces the need of microprocessors to operate at increasingly high clock frequencies. While a higher clock frequency generally results in increased processing power, its disadvantage is that it also increases power dissipation which results in higher device operating temperatures. By adopting the Vedic multiplier, microprocessors designers can easily circumvent these problems to avoid catastrophic device failures.
The processing power of multiplier can easily be increased by increasing the input and output data bus widths since it has a quite a regular structure. Due to its
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regular structure, it can be easily layout in a silicon chip.
The Multiplier has the advantage that as the number of bits increases, gate delay and area increases very slowly as compared to other multipliers. Therefore it is time, space and power efficient. It is demonstrated that this architecture is quite efficient in terms of silicon area/speed.
Multiplication of two decimal numbers- 325*738:
To illustrate this multiplication scheme, let us consider the multiplication of two decimal numbers (325 * 738).
Line diagram for the multiplication is shown in fig2.1.
The digits on the both sides of the line are multiplied and added with the carry from the previous step. This generates one of the bits of the result and a carry. This carry is added in the next step and hence the process goes on. If more than one line are there in one step, all the results are added to the previous carry. In each step, least significant bit acts as the 7result bit and all other bits act as carry for the next step. Initially the carry is taken to be zero. To make the methodology more clear, an alternate illustration is given with the help of line diagrams in figure where the dots represent bit „0‟ or
„1‟ .
Figure 3Multiplication of two decimal numbers by Urdhva Tiryakbhyam
Consider an example of a 4x4-bit Vedicmultiplier unit as shown in Fig. 4 which multiplies two 4-bitnumbers (A and B), each number can be expressed as (A0–
A3,B0– B3); A3 and B3 being the most significant inputs.
Figure 44x4 bit Vedic multiplication method Each square shape block in the above figure shows a 2x2bit Vedic multiplier unit. First 2x2 bit Vedic
multiplier hasinputs as A1A0 and B1B0. The last block is also 2x2 bit Vedicmultiplier with inputs A3 A2 and B3 B2. The blocks in themiddle are 2x2 bit multipliers with inputs A3 A2 & B1B0 andA1A0 & B3 B2. So the final result of multiplication will be of 8bit as S7S6S5S4S3S2S1S0. To understand the concept, the Blockdiagram of 4x4 bit Vedic multiplier is shown in Fig. 5. To getfinal product (s7 s6 s5 s4 s3 s2 s1 s0), four 2x2 bit Vedicmultipliers and three 4-bit Ripple-Carry (RC) Adders arerequired.
Figure 5Block diagram of 4X4 bit Vedic multiplier Analysing 4X4 multiplications, inputs are a3-a0 and b3- b0and the output is given by s7 s6 s5 s4 s3 s2 s1 s0.The inputsof 1st 2X2 multiplier are a1a0 and b1b0, 2nd 2X2 multiplierare a1a0 and b3b2, 3rd 2X2 multiplier are a3a2 and b1b0 andthat of 4th 2X2 multiplier are a3a2 and b3b2.
As compared to Array Multiplier, Proposed VedicMultiplier is efficient in terms of delay and speed.
TheProposed Vedic Multiplier can be used to reduce Delay. This4X4 Multiplier Module is the Basic Building Block of 8X8Vedic Multiplier.
The module of 8X8 bit Vedic multiplier shown in Fig.
6can be implemented by using four 4X4 bit Vedic multipliermodules [12]. Analyzing 8X8 multiplications, inputs are a7-a0 and b7-b0 and the multiplication‘s 16 bits output will bes15-s0.In this , four 4X4 bit Vedic multipliers and three 8 bitRC Adders(having 2 input of 8 bits) are required. Inputs aregiven to the 4x4 bit Vedic multipliers and the output ofmultiplier is of 8 bits.
Now, the input of the 1st RC Adder isthe output of the 2nd and 3rd 4x4 bit multipliers which givesoutput of 8 bits (7-0) + one carry. The 2nd RC Adder will addthe output of 1st RC Adder (7-0) and 4 bits (7-4) output of 1st4x4 bit Vedic multiplier, other 4bit of are considered as 0.Sooutput is of 8-bits(7-0) and one carry(carry is discarded).
The 3rd RC Adder will add the output of 4th 4x4 bitmultiplier (7-0) and 4 bits of output of 2nd RC Adder (7-4),other 4 bits are carrying of 1st RC Adder and 0.Now, the outputof 8x8 multiplier is s(3-0) output of 1st 4x4 bit multiplier(3-0), s(7-4) is output of 2nd RC Adder (3-0) and s(15-8)=8 isoutput of 3rd RC Adder(7- 0).
Figure 6Block diagram of 8X8 bit Vedic multiplier
III. VEDIC MULTIPLIER USING MTCMOS AND POWER GATING
CMOS technology when scaled helps in the attainment ofreduced supply and threshold voltages. When the thresholdvoltages are lowered the sub threshold current begins to waxprecipitously. Leakage current plays a pivotal role in modernhigh performance integrated circuits (ICs) as more than 40%of the total active mode energy is associated with thesecurrents. Integrating more transistors on-chip, causes theleakage current to dominate the high performance IC‘s totalenergy consumption. Additionally, it is the leakage currentwhich is the prime source of energy consumption in an idlecircuit.
In various hand-held battery-operated gadgets like mobilephones, laptops etc. employs long standby periods thusreducing the leakage current is highly important to providelongevity to the battery. The highly recommended circuittechnique for the leakage current reduction is the Multi-Threshold Voltage CMOS (MTCMOS).
In MTCMOS technology, efficient power management isobtained by allowing the circuit to operate in two modes: 1)Active Mode 2) Sleep Mode. The conventional circuit worksusing a single threshold voltage (Vt) whereas the circuitsemploying the MTCMOS technique works on two differentthreshold voltage switches i.e. the Low Vt and High Vt . Thecircuit makes use of two different set of transistors – onebeing the High Vt transistors known as the ―sleep‖
transistors and other being the Low Vt transistors which forms the logical circuit. The sleep transistors helps in the reduction of leakage current thus providing the high performance and the Low Vttransistors are used to boost the circuit‘s speed performance.
Figure 7Power Gating Techniques using MTCMOS The Fig.7 shows the power gating technique used in MTCMOS. The above circuit consists of a sleep transistors S1 which possess the higher Vt . The logical circuit between S1 and ground comprises of the Low Vt transistorsis not connected directly to the real supply, Vdd,but is connected to virtual supply and Vdd. The sleep transistors are provided with complementary inputs S ..
The circuit works in the active mode when, S=0 thus making the sleep transistor S1 toremain ON and the virtual supply a Vddv works as real supply lines and the logic circuit performsits operations normally at higher speed. But when S=1 , the circuit works in the sleep mode making S1 sleep transistors to go in OFF state which results in the floating of virtual power supply lines and sleep transistors S1suppresses the large leakage current present in the circuit. This reduces the power consumption as the leakage current has been lowered and also power gating can be efficiently achieved with clock as criteria .Fig.8 represents the implementation of XNORusing the MTCMOS technique.
Here a high Vt transistor i.e.the sleep nMOS transistor is incorporated at the bottom of the logical circuit design which during the sleep mode helps inthe abatement of the leakage current present in the circuit thusreducing the overall power consumption.
Figure 8XNOR using MTCMOS Technique.
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IV. RESULTS AND CONCLUSIONS
This paper introduces a novel and high performance design of an 4x4 multiplier using ancient Indian mathematics called Vedas.We have presented three different designs of the 4x4 Vedic multiplier using the CMOS technology,and secondly the Vedic Multiplier usingthe Multi-Threshold Voltage CMOS (MTCMOS) and provedthat the power gating implementation of Vedic Multiplier is thebest among all the implementations.
The Below schematic represent the gate design of the proposed MT cmos multiplier .the schematic is drawn using DSCH software.
Figure 9Schematic of mt cmos multiplier
Figure 10 Simulation of the mt cmos vedic The above simulation is output of the mt cmos vedic multiplier as in fig 10 schematic .when the resultant output is zero the it shows a dontcare whereas if output is 1 it shows a red line indicating 1. .
Figure 11power gating paired with the proposed vedic multiplier
Figure 12 Simulation of the power gating vedic multiplier
The above power gating method is to run the circuit in the alternative clocks .
The multi threshold CMOS technology has two main parts. First, ―active‖ and ―sleep‖ operational modes are associated with MTCMOS technology, and the power gating methodology is dependent on the high voltage transistor connected to the vdd of the circuit.
Figure 13 power consumption
Figure 14delay of the TOP Module
Figure 13 and 14 shows the Layout and RTL Schematic of the Proposed System.
Fig 15. Hist graph regarding the power consumption The multiplier and theadder-subtractor units used for the implementation of Vedicmultiplier are adopted from ancient methodology of Indiamathematics called as Vedas. The use of Vedas not only abatesthe carry propagation taking place from lsb to msb but alsoproduces the partial product and there sums in the
same step.Vedic mathematics based multipliers thus causes least delay andconsume least power than any other type of multipliers in the literature. The functionality of all the three designs is tabulated and shown in the results .
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Authors Profile:
Pathan John Khan is pursuing his Master degree M.Tech in VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS in KKR
& KSR Institute of Technology & Science.
B. Nageswara Rao Naik is working as Assistant Professor in KKR & KSR Institute of Technology &
Science.. he has over 6 years of Teaching experience.
