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Recent Status and Key Issues in Fault testing of Reversible Circuits:
An Emperical Analysis
1Sanjoy Mitra, 2Debaprasad Das
1Dept. of Computer Science and Engineering, Assam University, Silchar, Assam, India-788011
2Dept. of Electronics and Communication, Assam University, Silchar, Assam, India-788011
Abstract— Reversible computing has the remarkable ability of managing energy loss in digital circuits and owing to this tremendous ability, it has drawn the major attention of both academic and industrial research community. Hence, testability of such systems crops up as an important arena of research. Advancements in fault diagnosis-testing techniques are on ramp to uncover faults present in reversible circuits in a more efficient way in order to integrate higher reliability in reversible computation.
In this paper, we have drawn illuminating comparison of state of the art fault testing approaches along with fault models and also analyzed focal issues in this context.
Keywords: reversible gates; testability; faults
I. INTRODUCTION
Low cost choice to conventional computing in terms of power consumption, speed and computing efficacy has become a critical issue in digital circuit design. In logical computation, energy is dissipated for every bit of lost information irrespective of the technology selected for implementation [1]. Ideally, reversible computing has the ability of processing information in a nearly lossless manner and theoretically states zero power dissipation. In recent times, it has emerged as a flourishing research Energy dissipated due to information destruction during carrying computing and superconductor flux logic family is a momentous factor of the overall heat dissipation .Besides, reversible computations are also deemed as a special class of quantum circuits. Quantum computations are exponentially quicker than conventional computations.
It can accomplish huge parallel computations in a single step and solve many problems such as prime factorization with less time complexity than that of non- quantum approaches [2, 3] .The quantity of energy dissipated in a system bears a direct kinship to the number of bits expunged during the computation. The energy required for binary transition Ebitis given by the Shannon–Von-Neumann–Landauer (SNL)expression[6],
eV .
= T = K E
Ebit SNL B ln2 0017
where KB is the Boltzmann constant, T=300 K. This is the minimum energy required to process a bit. Whenever a physical system flings out information about its previous state it must produce a analogous measure of entropy. Landauer [1] attested that for irreversible logic computations, a single bit loss results in dissipation of KBT ln2 Joules of heat energy. Further, Bennett [5]
shown that the KBT ln2 energy dissipation cannot happen if a computation is taken away in a reversible way. Reversibility in computing entails that information relevant to the computational states can never be lost and any earlier stage can be convalesced by computing rearwards or un-counting the results. Thus, one of the most important motivations for adopting reversible logic lies in the fact that it can provide a logic design methodology for designing ultralow power circuits beyond KBTln2 limit for those emerging nano-circuits where the energy dissipated due to information destruction will be a major aspect of the overall heat dissipation [43, 10].
Test automation of reversible circuits have attracted as a major research challenge. Researchers have worked on various facets of reversible logic testing, such as fault modeling, test pattern generation etc. Here in this paper we review a number of diverse approaches of fault testing of reversible circuits reported in the literature and explores the key issues regarding their designs on error detection.
The remainder of this paper is structured as follows:
Section II briefly introduces the required basics on reversible logic circuits and reversible logic gate. After this, a comprehensive review on testing methodologies are presented in Section III. Section IV deals with performance evaluation metrics of reversible circuit testing. Methodology and fault models are described in Section V and finally conclusions are derived in Section VI
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II. REVERSIBLE CIRCUIT BASICS
A. Reversible Logic
An n-input and m-output Boolean function F is said to be reversible if and only if m = n, and F is one-to-one.
Alternatively, we can say that a reversible function produces outputs by simply inducing a permutation on the set of input vectors. In this model of computation, corresponding input vector can be uniquely restored from a given output vector.
B. Reversible Logic Circuit
A reversible logic circuit RC of size n with depth d is formed by cascading d reversible gates on the set of
input lines
x x x x x xn
X 1, 2, 3, 4, 5... i.e.,RCg0g1g2...gd1, here each gi represent ithreversible gate of the circuit RC. A combinational logic circuit is called reversible if it is fan-out free, acyclic, and consists of only reversible gates upon which they implement reversible functions.
Such gates are specially designed, e.g., Toffoli gates.
Most of the conventional logic gates except NOT, are irreversible.
C. Garbage
A garbage output of a reversible circuit is defined as the additional output whose functional response is not an ingredient of design specification. Some outputs are required to keep up the reversibility property but none of them have turned up as final results and used for subsequent computations. Such outputs are called garbage outputs.
D. Reversible Gates
A reversible gate is defined as g(C,T) whereCxi1,xi2,xi3...xikis called the set of control lines and T xj1,xj2,xj3...xjkis the set of target lines withCT. In reversible gate, the control set C may be empty but T contains as a minimum one target line. When the value of control lines satisfies the required control conditions, then the operation of gate is applied to the target lines. After gate operation, the outputs of control lines and unconnected lines of any reversible gate always are same with their relevant input values.
E. Fundamental Reversible Gates
The basic reversible gates are namely 1-input/1-output NOT, 2-input/2-output controlled NOT (CNOT),3- input/3-output Toffoli gate ,Fredkin gate , Swap gate ,Peres gate and TR gate
In addition to the above, there exist many reversible logic gates in the literature. Among them 22 Feynman gate (FG) [7], depicted in Fig. 1, 33 Peres gate (PG) [10], 33 Toffoli gate (TG) [8], and 33 Fredkin gate (FRG) [9], have been studied extensively.
Fig.1.Examples of 22 Feynman Gate, 33 Peres Gate, 33 Toffoli Gate and 33 Fredkin Gate
III. TESTING APPROACHES IN REVERSIBLE CIRCUIT
Realizing integrated reversible circuits formulates controllability and observability declined and so verification and testing of system becomes mammoth challenge. Various techniques are presented in literature for fault testing of reversible circuits. These are classified into two broad spectrum namely offline and online testing approaches.
Offline approaches are known to perform fault testing in extra time by means of a predefined test set whereas online version do this in normal operation using a normal input vector. Offline testing presumes that the circuit will be taken out of usual operations and can be tested by applying a number of test vectors for which the correct output values for the circuit are known [11]. So,
a key issue in determining offline testing approaches for a specific fault model is the development of test sets that are complete for the model under contemplation. A test- set is called complete if it is capable of detecting all faults in the fault set F and if this set contains the least probable vectors then the set is called minimal [12].
Fig.2 Major two subclasses of fault testing strategies
Fig.3 Online testing approaches of reversible circuit.
Fig.4 Offline testing approaches of reversible circuit.
Online approaches of testing for reversible circuits available in literature include testable circuits based on R1, R2 and R3 gates [13, 14], based on testable reversible cells (TRCs) [15], based on online testable gates (OTGs) [16], dual-rail reversible gates [17, 18], parity-preserving reversible gates [6, 19, 20] and based on extended Toffoli gates (ETGs) [21, 22] respectively.
These approaches except ETG based [21, 22] are further categorized as parity-generating [13-16], parity- preserving [6, 19, 20] and dual rail online error detection methods [17, 18]. On the basis of results of [21, 22], the methods based on ETG are far superior to others in terms of quantum cost and garbage‟s generated.
Other methods of fault testing for reversible circuits mostly include ILP [23], ATPG [24-27] and DFT [14, 28, 30, 43] method. ILP method presented test-set
constructions for the standard stuck-at fault model as an integer linear program with binary variables but this is invalid for missing-gate fault and miss-control fault.
ATPG method gave miss-control fault model. DFT method can detect missing-gate fault and bridging fault by generating a complete test-set. DFT approaches increase hardware cost by adding extra gates and the required quantity of such extra components is above the half of the number of primitive gates necessary for functional circuit implementation. This increases hardware costs heavily and may lead to new faults. D. P.
Vasudevan[14] introduced two new types of reversible logic gates in order to realize testable reversible logic gates. Noor Mahammad contributed enhancements to the above approach and incorporated TRC reversible realization to solve testing problem [30]. However, this approach too became overburdened by extra hardware overhead,
IV. PERFORMANCE EVALUATION METRICS
In literature, many testing schemes for reversible circuit are presented based on variety of parameters. Some of them work in online mode and other in offline mode.
Irrespective of the approach used for testing of faults, some common attributes need to be defined to achieve distinctiveness in performance rating. Some of them can be defined as following.
F. Fault Coverage
Percentage of faults detected out of the total number of faults present in the modeled fault set.
G. Test Coverage
Percentage of faults detected from the list of detectable faults.
H. Garbage Output
Garbage outputs increase the number of lines in a circuit and hence increase the width of the circuit. It is more important to reduce the garbage outputs than the number of gates [31, 14].Minimization of the number of required garbage outputs of a circuit is a challenging assignment while designing reversible circuit.
I. Path Delay
The path delay is the cumulative effect of the delays occurred along a path in any reversible circuit If the cumulative delay surpasses the clock period for the path, then the test pattern that fails the chip is said to sense the path delay fault.
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J. Gate Count
It is the simplest way to compare and evaluate testing cost associated with diverse design for testability techniques. It refers to the number of gates required to realize the circuit. Type of the gates and number of bits in the gates used in the circuit are similar [32].
K. Quantum Cost
The computation of quantum cost [33, 34]
corresponding to any reversible gate is determined by finding the implementation specific quantity of one-bit and two-bit quantum gates from a universal gate set.
The cost of the circuit may be computed more accurately by summing up quantum cost of all gates in the circuit or by finding quantum cost of the whole circuit. The quantum costs of different generalized Toffoli gates may be seen in Maslov‟s reversible benchmarks page [36].
Improved quantum cost for n-bit Toffoli gates was discussed by D. Maslov and G.W. Dueck in [35].
L. Time Overhead
Runtime is widely used to assess the efficiency of different testing algorithms. It is often used to compare the performance among a variety of testing approaches.
V. FAULT MODELS
A fault model simplifies the analysis and complexity of testing by reducing the number of defects those have to be considered. Depending on the number of faults in a circuit, fault models can be categorized as single fault models and multiple faults models. The single fault model considers only one fault in a circuit whereas multiple faults model deals with several faults.
The models vary in accordance with the type of description that is being incorporated, which in turn varies according to the level of abstraction. These are the currently proposed fault models for reversible circuitry.
There are many places that a fault could be located in a circuit, and it is hard to determine at which places errors would be likely to occur because there does not exist a commonly agreed upon technology for building reversible circuitry.
M. The Stuck at Fault Model
It considers that the span of this type of fault is restricted to one of the horizontal wires on the circuit only. A transient bit can either get stuck at value zero or may stuck at value one. A stuck-at fault in a logic gate causes one of its inputs or outputs to be stuck either at a logic value 0 (stuck-at-0) or at a logic value 1 (stuck-at-1), irrespective of the inputs of the circuit. This fault model annihilates the reversibility of a circuit, since data is lost as it passes over the fault
N. Bit Fault Model
The bit fault model has been considered in various articles such as [52, 21, 22]. In this model, gate‟s output behavior is influenced by the presence of fault in that gate A single bit fault is reflected to stuck-at fault sets the output of a gate to either 0 or 1, whereas a bit fault flips the output of a gate (from 0 to 1 or vice versa).
Unlike the stuck-at fault model, this model depends on the input values.
O. Missing, Repeated and Reduced Gate Fault Models Hayes et al. [44] proposed three new fault models namely missing gate, repeated gate, and reduced gate fault models. A brief discussion is given below in subsequent articles:
a. Missing Gate Fault Model
In this fault model, a gate is completely disappeared from a circuit and replaced by simple wire connections.
b. Repeated Gate Fault Model
Gate duplication in a circuit causes this fault to occur c. Reduced Gate Fault Model
If the output of a gate computes a partial function, this type of fault occurs.
P. Cross Point Fault Model
In [45], Zhong and Muzio proposed the cross-point fault model for Toffoli gates. A cross point fault occurs if the existing controls of a Toffoli gate do not work properly or if extra control points change the behavior of a Toffoli gate. Such faults can therefore be classified as disappearance faults or appearance faults. A disappearance fault removes one or more control points from a Toffoli gate and consequently, the number of bits in the gate is also lessened. An appearance fault introduces one or more additional control points to a Toffoli gate, increasing the number of bits in the gate.
VI. CONCLUSION
In this paper, we have reviewed the fundamental concepts, performance measures and other significant parameters that impact testing of reversible circuits. In this paper we have reviewed previous approaches for testing of reversible circuits and discussed their design issues and limitations. The extensive analysis and comparisons based on benchmark circuits corresponding to different fault testing approaches are also shown in this paper. In the comparative literature presented earlier, some of the important aspects that contribute to testing methodologies of reversible circuits such as optimum utilization of reversibility property during
testing algorithm development, testing performance quality metrics etc. are relatively less investigated.
Hence, we have focused on such issues. Different methodologies to conduct testing and their key features are pointed out. Thus, optimum utilization of reversibility property, selection of test case specific fault model and use of appropriate testing algorithm will result in high accuracy automated testing system.
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Fig.5 Fault Models.
Table 1: Comparison of different fault testing approaches
Testing scheme Fault Coverage (% & fault type) Quantum Cost Garbage Output
[37] About 5% improvement from
existing, missing control fault
This realization is not available
This realization is not available
[38] 100% fault coverage for single missing /additional cell defect in QCA layout of the Fredkin gate
4 & 5 nos. for T and D flip flop respectively in Test mode
[39] PGMF, SGMF & RGF Increase in quantum cost was reduced by 87.53%
Not realized
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on an average in comparison to [24]
[40] PGMF, SGMF & RGF Increase in quantum cost was reduced by 119.38%
on an average in comparison to [24]
Not realized
[41] Not realized Improvement over [22] &
[21] in terms of quantum cost by 16.07% &
95.15% respectively on 10 benchmark circuits
[42] About 2.04% reduced About 25%reduction
Table 2 – Review of major approaches of Fault Testing of Reversible Circuits
Algorithm Fault Type(s) Key Features
[37] Missing Control The algorithm executes in linear time
Fault diagnosis tree is constructed from the unique fault signatures for every missing control and through tree traversing each fault is diagnosed.
Equivalent faults are also detected
[23] Multiple stuck at fault An integer linear program (ILP) formulation, with binary variables used to minimize the test set
The method is suitable for small circuits and can be applied to large circuits using decomposition techniques
[29] Missing gate Higher testability of missing gate faults
Easily determinable test set
a simple design-for-test (DFT) method to make any reversible circuit fully testable for MGFs with the help of single test vector
[14] Single bit output error Provides online testability
Detection of single bit output error by the built-in parity.
[46] Stuck at faults Faults are detected and located with the help of a symmetric adaptive tree
Easier fault localization
[47] Single SMGF/RGF A new testing technique namely Ping Pong test was proposed
Reduction of information requisite for achieving high fault coverage (100%)
Reduced test data volume [48] Missing Gate fault &
Bridging Fault
Low power & smaller area size DFT technique
Garbage lines are utilized for testing [42] Single bit error inclusive
of soft errors in the logic block
Testable circuit with minimum garbage
Automatically converts any given reversible circuit into an online testable circuit
[49] Unidirectional stuck at fault
Increased programmability
Single stuck at faults at reversible arithmetic logic unit(RLU) and reversible arithmetic unit(RAU) can be tested with two test vectors only.
Concurrent testing strategy [50] Multiple missing gate
faults
Search tree formed by input output permutation of basic gates used to derive the minimal test set.
Same test set is also used for detecting SGMF & RGF [51] Missing gate,
Control point appearance / disappearance
A reversible test meter capable of backtracking is designed to uncover error
Testing scheme is based on Boolean satisfiability(SAT)
Test set size reduced
Increased fault coverage & testing speed.
[52] Single missing-gate fault (SMGF)location
Algorithms namely LRCMD and MSDA are proposed to locate fault into a small module.
These algorithms give good performance in localization of single missing-gate fault
Table 3:- Comparison of some online testing approaches Online Testing
Approach
Techniques Merits Demerits
Testable Circuit Design Using R1, R2, and R Gates
[14] The testable circuit has a quantum cost of 56 and 12 garbage outputs.
The overheads are 250 % and 300 % in terms of quantum cost and garbage outputs, respectively, compared to the non-testable circuit
A close investigation reveals that this approach cannot detect all single bit faults. If a fault occurs between two Testing Blocks, the circuit is unable to detect it.
Testable Circuit Design Using Testable
Reversible Cells (TRC)s
[42] This testable circuit has a 8 garbage outputs
The overheads are 143.75 % and 166.67 % in terms of quantum cost and garbage outputs, respectively, compared to the non-testable circuit.
Fault between the connections of two TRCs in is undetectable.
Testable Circuit Design Using Online Testable Gates
[16] 4×4 reversible online testable gate (OTG) introduced in their The checker circuit using four 3-bit Toffoli gates and two 3-bit Fredkin gates
This testable circuit has a quantum cost of 52. The overheads are 225 % and 300 % in terms of quantum cost and garbage outputs, respectively, compared to the non-testable circuit
This approach also fails to detect a fault that occurs between two blocks.
Dual Rail Coding Approach
[17] In this approach does not need a checker circuit for fault propagation and
testing of
intermediate gates This approach can detect any single bit fault in the circuit It also produces 5 garbage outputs
The quantum cost of this circuit is 126. Thus the overheads are 687.5 % and 66.67 % in terms of quantum cost and garbage outputs, respectively.
Testable Circuit Design with Duplication of Gates
[53] This approach can detect any single missing gate fault
The testable circuit implemented in this way requires 4 times as many gates as the non-testable design requires.
The complexity of this technique in terms of quantum cost is 2g +2q, where g and q are the gate count and quantum cost of the non-testable design, respectively.
Testable Circuit Design with Preamble Block ,Duplication of Block & Post amble block
[54] This approach results in lower overhead for circuits with a larger number of gates
This approach cannot detect a single bit fault if the fault occurs in the Preamble Block.
This approach fails to detect multiple missing gate fault.
Table 4:Comparison of quantum cost overhead among different testable circuit designs Benchmark
Circuit
Quantum Cost In [14]
Quantum Cost In [17]
Quantum Cost In [42]
Quantum Cost In [16]
Quantum Cost In [54]
rd32 873 1257 110 869 24
ham7 5861 8367 653 5857 112
rd53 15470 20583 1632 15486 478
alu2 40992 52500 6549 40988 …
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alu4 132367 169332 63165 132363 …
apex5 195061 213843 69569 195057 …
apla 17815 20574 5457 17811 …
bw 19019 25140 8757 19015 …
c17 486 564 190 482 …
cm82a 2163 2823 370 2159 …
