Rapid methods are focused on finding faster protein sequence analysis for database scanning and accurate protein identification. Machine-accelerated protein identification solutions are being used to address bottlenecks in the computational biology pipeline. Once all the peptides of an unknown protein have been searched, we can assign a score to the proteins in the database to find the one that best matches the unknown protein we are trying to identify.
Efficient substring search algorithms such as Boyer-Moore[2] and Knuth-Morris-Pratt [3] that locate single pattern strings within a larger text string can be used in a multiplex fashion (i.e. one match for each string in the set of peptides ). The Aho-Corasick algorithm [4] provides a scalable solution to the string set matching problem by incorporating the search mechanism for the entire set of patterns into a single finite state machine (FSM). The power of Aho-Corasick stems from the ability of the algorithm to find the location of the strings in the pattern set in the text string in a single pass.
The computational complexity of the Aho-Corasick search is O(m + k) where k is the total number of occurrences of the pattern strings in the text. This linear processing time complexity has resulted in the widespread use of Aho-Corasick in string matching applications. Rapid methods focus on the search for faster protein sequence analysis to scan databases and accurately identify a protein [9].
The Aho Corasick (ACA) algorithm is a commonly used multi-pattern string matching algorithm that has linear computational complexity [4][12].
Theoretical Background
Aho-Corasick, matching the peptide set {ACACD, ACE, and CAC}; Table 1 shows a table-oriented representation used to implement the same FSM. In Figure 1, state 0 is the initial state and the shaded states 4, 5, 6 and 9 Match peptides CAC, ACACD, ACE and CAC respectively. When the FSM is in any state and receives an input symbol not shown in the figure, the FSM transitions to state 0.
At runtime, the FSM interpreter reads the row corresponding to the current state from the table, reads the next input symbol from the read frame, and determines the next state from the row entry corresponding to the input symbol. When the FSM enters the as state, it looks in the pattern match column of the corresponding row of the table to determine if a match has occurred. A non-null entry in the row pattern match entry specifies the pattern that is set by the FSM.
Pseudo Code for ACA FSM Implementation
Above algorithm implementation creates FSM table for peptides ACACD, ACE, CAC as shown in table-1 above. The above algorithm of FSM table is implemented in C language, which is the software part of our Hardware Software Co-Design. The above table is stored in BRAM of Xilinx ZYNQ FPGA and it is connected with generic custom IP so that it forms the FSM logic in hardware.
The FSM logic hardware is implemented in the PL (Programmable Logic) section of the Xilinx Zed Board and is controlled by the ZYNQ processor which is in the PS (Processing System) section of the ZYNC-7000 SOC.
Proposed Methodology
The AXI block RAM (BRAM) controller acts as a bridge to the block memory generator module used to generate block memory. The AXI block RAM (BRAM) controller acts as a bridge to communicate between the ZYNQ7 via the AXI interconnect and the BRAM created by the block memory generator. Custom hardware module is the necessary hardware logic required to realize FSM using memory communication between ZYNQ7 via AXI interconnect and BRAM created by block memory generator.
A detailed diagram of the interface between block memory and hardware logic is shown in Fig. Block memory is stored with contents that implement the Aho-Corasick algorithm with hardware logic. A status register is used to latch the output of the multiplexer and feeds the block memory generator with the required address.
Vivado Design Suite has all the features of a hardware system design along with system on a chip development. We use the Creating and Packaging Custom IP tool available in Vivado to design the hardware logic as depicted in Fig. The onboard FPGA device is configured with the bitstream file along with the application program.
We use the memory-based architecture to implement the FSM proposed in [20][21] and generate the block RAM contents for the corresponding FSM and store them in the block RAM. The database file in which the patterns are searched is read from the SDHC card and the characters are received by custom hardware. These characters act as block memory addresses and the data stored at these addresses are available from the block memory.
The input of the multiplexer is connected to this data and a part of this data is selected depending on the character entered in the custom hardware. The output match vector is also part of the data and provides information about the pattern found after retrieving the characters. The system runs until the end of the database file. The UniProt (Universal Protein Resource) identifier for the protein in which the patterns are found along with their corresponding location in that protein is displayed in a console window.
Results and Discussions
Conclusion
Theoretical Background
Then, all the states in the original FSM that can be reached by FSM:0 (Root Node from the original FSM) when the transition bit position is 0 are determined and accumulated in a new bit allocation node FSM0:1. Because FSM0:1 does not already exist in FSM0 (that is, there is no state in FSM0 that is aggregated from FSM:1 and FSM:7), it is added to FSM0 with a transition from FSM0:0 when the input bit is 0 Then, all states in the original FSM that can be reached by FSM:0 when the transition bit position is 1 are determined and accumulated; in this example, there are no such states.
Therefore, the transition from FSM0:0 goes back to FSM0:0 when the input bit is 1. This process is repeated for all newly added states in FSM0. Therefore, all states in the original FSM that can be reached from either FSM:1 or FSM:7 when the input at the bit position is 0 are aggregated to FSM0:2. Because FSM0:2 does not already exist in FSM0, it is added to FSM0 with a transient of 0 from FSM0:1.
Again, there is no transition from FSM0:1 when the input bit is 1, therefore state FSM0:1 goes back to FSM0:0 when the input bit is 1. This process continues until no new states are added to FSM0. Peptide matches are also handled using aggregation (ie, state FSM0:k matches all the peptides matched by states in the original FSM that were aggregated to FSM0:k). This process is repeated for all bit positions, resulting in the five separate bitwise FSMs tabulated in Tables and 9.
Because several states from the original FSM that match different peptides can be combined into a single state in a bitwise FSM, a mechanism to indicate multiple matches is required. In bitwise FSM, a vector of bits is used to encode the peptide match attribute for each state. The bitwise logical AND of the five match bit vectors results in bit vector 100 indicating that peptide 3 matches in this case.
The Block diagram of the system is presented below which accelerates the pattern matching of peptides by exploiting bit level parallelism 5-bit split FSM and the memory consumption of the design is low compared to ACA FSM. In the above Bit Split Algorithm Implementation, we have given the idea about the system design we envisioned. In this thesis I proposed a reconfigurable hardware-software co-design methodology for protein identification which has real-time application for bioinformatics research and I also gave the idea about the hardware-software co-design of Bit Split Algorithm A system design approach that provides a parallel architecture that can further accelerate the protein identification with less memory consumption.
Stults, "Protein identification: the origins of peptide mass fingerprints," Journal of the American Society for Mass Spectrometry, Vol. 25] Jung HJ, Baker ZK, Prasanna VK: Performance of FPGA Implementation of Bit-split Architecture for Intrusion Detection Systems.
Pseudo Code for Bit Split ACA FSM Implementation
Future work
The above system can be implemented on Real-time Xilinx Zync FPGA by introducing the concept of Hardware Software Co-Design with reconfigurability and parallel architecture by utilizing the concept of bit-level parallelism with less memory consumption. With all these advantages, the system can be used to accelerate bioinformatics research in protein identification, which has numerous biomedical applications. 5] Tan L, Sherwood T: A high-throughput string-matching architecture for intrusion detection and prevention: Madison, Wisconsin, USA. Hogue, "Hardware Accelerated Novel Protein Identification", Field Programmable Logic and Application - Lecture Notes in Computer Science, vol.
8] Jian Zhang, McQuillan I., Fang Xiang Wu, "Speed improvements of peptide spectrum matching using SIMD instructions", Bioinformatics and Biomedicine Workshops (BIBMW), 83-88, Dec. 14] Brudno M, Steinkamp R, Morgenstern B: The CHAOS/DIALIGNWWW server for multiple alignment of genomic sequences.Nucleic Acids Res 2004, 32 (Web Server Edition):W41-4. 17] Michael M, Dieterich C, Vingron M: SITEBLAST--rapid and sensitive local alignment of genomic sequences using motif anchors.
Garcia-Vargas et al., "Rom-based finite state machine implementation in low-cost fpgas," in Industrial Electronics, 2007ISIE 2007.
