A BIDIRECTIONAL AREA AND SPEED OPTIMIZED INTERFACING BRIDGE BETWEEN ADVANCED HIGH PERFORMANCE AXI BUS WITH AHB BUS IN SOC
1Nishtha Ledwani,
Gyan Ganga College of Technology, Jabalpur
2Guide: Prof. Sunil Shah,
Gyan Ganga College of Technology, Jabalpur 1. INTRODUCTION
1.1 AMBA Specifications
The Advanced Microcontroller Bus Architecture (AMBA) detail characterizes an on chip correspondences standard for planning elite implanted microcontrollers.
AMBA detail has been inferred to fulfill four key necessities:-
1. To limit silicon framework required to help effective on-chip & off-chip correspondence for both activity &
assembling test.
2. To be innovation autonomous &
guarantee that profoundly reusable fringe & framework large scale cells might be moved over a differing scope of IC forms & be proper for full-custom, standard cell & door exhibit advancements.
3. To encourage right-first-time improvement of implanted microcontroller items with one or parcel CPUs or sign processors.
4. To urge secluded framework configuration to improve processor freedom, giving an advancement guide to cutting edge reserved CPU centers & advancement of fringe libraries
Two particular rapid transports are characterized inside AMBA determination for above detail:-
1. The Advanced High-execution Bus (AXI)
2. The Advanced Peripheral Bus (AHB).
1.1.1 Advanced High Performance Bus (AXI): AMBA AXI is for elite, high clock recurrence framework modules. AXI goes about as elite framework spine transport.
AXI bolsters proficient association of processors, on-chip recollections & off- chip outer memory interfaces with low- control fringe large scale cell capacities.
AXI is additionally determined to guarantee convenience in an effective structure stream utilizing amalgamation
& computerized test strategies.
1.1.2 Advanced Peripheral Bus (AHB):
AMBA AHB is for low-control peripherals.
AMBA AHB is enhanced for insignificant power utilization & decreased interface intricacy to help fringe capacities. AHB might be utilized related to either form of framework transport.
1.2 AMBA Terminology
The accompanying terms are utilized all through this detail.
1.2.1 Burst Activity: A burst activity is characterized as one or parcel information exchanges, started by a transport ace, which have a predictable width of exchange to a steady locale of location space. addition step per exchange is controlled by width of exchange (byte, half word, & word). No burst activity is bolstered on AHB.
1.2.2 Bus Cycle: A transport cycle is an essential unit of one transport clock period & for reason for AMBA AXI or AHB convention depictions is characterized from rising-edge to rising-edge changes.
An ASB transport cycle is characterized from falling-edge to falling-edge advances.
Transport sign planning is referenced to transport cycle clock.
1.2.3 Bus Move: An AMBA ASB or AXI transport move is a perused or compose activity of an information object, which may take one or part transport cycles.
bust Transfer is ended by a finish reaction from tended to slave. move sizes bolstered by AMBA ASB incorporate byte (8-bit), half word (16-bit) & word (32-bit). AMBA AXI also bolsters more extensive information moves, including 64-bit &
128-piece moves. An AMBA AHB transport move is a perused or composes activity of an information object, which constantly fundamental two transport cycles.
2. LANGUAGE & TOOLS
2.1 Overview of Xilinx ISE Software The ISE Design Suite is central electronic design automation (EDA) product family sold by Xilinx. ISE Design Suite features include design entry & synthesis supporting Verilog or VHDL, place-and- route (PAR), completed verification &
debug & creation of bit files that are used to configure chip. The ISE® software controls all aspects of design flow.
Through Project Navigator interface, you may access all of design entry & design implementation tools. You may also access files & documents associated with your project.
Project Navigator Interface: By default, Project Navigator interface is divided into four panel sub-windows; on top left are Start, Design, Files, &
Libraries panels, which include Display &
access to source files in project as well as access to running processes for currently selected source.
The Start panel provides quick access to opening projects as well as frequently access reference material, documentation & tutorials. At bottom of Project Navigator are Console, Errors, &
Warnings panels, which display status messages, errors, & warnings. Design Summary/Report Viewer: Design Summary provides a summary of key design data as well as access to all of messages & detailed reports from synthesis & implementation tools.
Summary lists high-level information about your project, including overview information, a device utilization summary, performance data gathered from Place & Route (PAR) report, constraints information, & summary information from all reports with links to individual reports. A link to System Settings report provides information on environment variables & tool settings used during design implementation.
Simulation tool: Xilinx® ISE Simulator (ISim) is a Hardware Description Language (HDL) simulator that enables you to perform functional (behavioral) & timing simulations for VHDL, Verilog & mixed-language designs.
basic simulation flow. Synthesis tool:
Xilinx XST is used to synthesis various modules. It comprises tools that synthesize HDL designs into optimized
technology-dependent, gate-level designs.
It supports a wide range of hierarchical design styles & may optimize both combinational & sequential designs for speed, area, & power.
Power tool: This thesis involves usage of XPower Analyzer tools. XPower Analyzer tools offer power study &
optimization throughout design cycle, from RTL to gate level. Analyzing power early in design cycle may significantly affect quality of design. Improvements made to design while it is at RTL level may get even better results eventually.
Not only these power tools do accurate measurements however also may help in calculating power quicker.
2.2 Target Device
The target device used is Xilinx’s XCPQ208. Spartan-3 families of Field- Programmable Gate Arrays is specifically designed to meet needs of high volume, cost-sensitive consumer electronic applications.
3. LITRETURE REVIEW
Ckristian Duran et al [2] ARM avaialble IPs must have capacity to speak with AMBA 4.0 Data. In light of AMBA 4.0 Data, we composed an Intellectual Property (IP) center of Advanced Peripheral Bus (AHB) Bridge, which interprets AXI4.0-lite exchanges into AHB 4.0 exchanges. Scaffold gives an interface in-between superior AXI Data & low- control AHB space.
In this paper a total execution &
plan of a completely combined 32-bit microcontroller in a 65nm vertex innovation is exhibited. This is main microcontroller including open source RISC-V direction set all mounted through AXI4-Lite & AHB Datas for correspondence prepare.
Microcontroller contains a 10-bit SAR ADC, a 12-bit DAC, a 8-bit GPIO module, a 4kB-RAM, a SPI AXI slave interface for yield confirmation, & a SPI AHB slave interface for checking right behavioral of AHB connect. All peripherals are controlled by a RISC-V & a SPI AXI ace interface that is utilized for programming gadget & checking information moving through every one of slaves. An aggregate power thickness is
accounted for as 167_W/MHz & range for this RISC-V microcontroller.
4. AMBA PROTOCOLS 4.1 Bus Interconnection
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Figure 4.1: Multiplexor interconnection 4.2 Basic Transfer
An AXI move comprises of two particular areas:-
1. The location stage, which keeps going just a solitary cycle.
Information stage, which may require a few cycles. This is accomplished utilizing HREADY signal.
2. In a simple exchange with no hold up states: ace drives address &
control signals onto transport subsequent to rising edge of HCLK.
The slave at that point tests address &
control data on next rising edge of clock.
After slave has examined address &
control it might begin to drive proper reaction & this is inspected by transport ace on third rising edge of clock.
Figure 4.2: Easy TRANSFER This simple model exhibits how address &
information periods of exchange happen during different clock periods. Indeed, address period of any exchange happens during information period of past exchange. This covering of location &
information is central to pipelined nature
of transport & takes into consideration elite activity, while as yet giving sufficient time to a captive to give reaction to an exchange. A slave may embed hold up states into any exchange, which broadens move permitting extra time for consummation.
Figure 4.3: Multiple transfers 5. METHODOLOGY
5.1 Available Work & Its Methods 5.1.1 Nikhil Gaikwad [1] work: in figure 5.1 below it may be clearly monitor that they are using a AXI2AHB Bridge in-
between AHB based slow speed devices &
AXI based High speed processor components, they use a fix size FIFO (pipe type) for interfacing.
Figure 5.1: AXI2AHB Bridge interfacing by Nikhil Gaikwad [1]
In figure 5.2 below AXI2 AHB bridge of by Nikhil Gaikwad et al [1] they have used Non FSM based control unit which
controls time slice mixer which is used for interfacing slow speed data from AHB on high speed AXI.
Figure 5.2: AXI2AHB Bridge by Nikhil Gaikwad [1]
5.1.2 Ckristian Duran [2] Work
Figure 5.3: AXI2AHB Bridge interfacing by Ckristian Duran [2]
In figure 5.3 above it may be clearly monitor that they are using a AXI2AHB Bridge in-between AHB based slow speed
devices & AXI based High speed processor components, they use FSM controlled FIFO for interfacing.
Figure 5.4: AXI2AHB Bridge by Ckristian Duran [2]
In figure 5.4 above AXI2 AHB bridge of by Ckristian Duran [2] they have used FSM based control unit which controls time slice mixer which is used for interfacing slow speed data from AHB on high speed AXI.
5.1.3 Chenghai Ma [3] Work
In figure 5.5 below it may be clearly monitor that they are using a AXI2AHB Bridge in-between AHB based slow speed devices & AXI based High speed processor components, they use FSM controlled FIFO for interfacing & DPRAM for full duplex communication.
Figure 5.5: AXI2AHB Bridge interfacing by Chenghai Ma [3]
6. RESULTS
6.1 Results Obtained
We are optimizing area & seed both that’s why design goal is balanced.
Figure 6.1: Synthesis Result
Timing Summary:-
1. Timing Summary: Speed Grade:- 11
2. Minimum period: 2.589ns
(Maximum Frequency:-
316.250MHz)
3. Minimum input arrival time before clock:- 3.927ns
4. Maximum output required time after clock: 5.057ns
5. Maximum combinational path delay:- 5.946ns
Total 5.946ns (4.634ns logic, 1.312ns route) (77.9% logic, 22.1% route) Table’s below shows synthesis results of presented work. Device: xc4vlx200- 11ff1513 (Vertex -4 FPGA)
Table 6.1 synthesis results obtain
Number of Slices 57 out of 89088 0%
Number of 4 input LUTs 111 out of 178176 0%
Number of bonded IOBs 238 out of 960 24%
IOB Flip Flops 49 out of 178176 0%
Number of GCLKs 1 out of 32 3%
Figure 6.2 below shows logical representation of presented design. In RTL result it may be clearly monitor all hierarchy maintained also AXI signal &
AHB signals at top level of abstraction. All interconnect of sub-modules in RTL are connected it shows correct abstraction &
signal flow of presented work. An extended RTL design of presented work is shown in figure 6.3 it has all connections
& all internal module available means correct coding & design is synthesis properly no any open element found in design.
Figure 6.2: RTL Top View
Figure 6.3: RTL Internal View Simulation of presented work is shown in
figure 6.4 below, Here in simulation we may easily monitor that we have two various speed clock high speed clock for
AXI & slow clock for AHB & still AXI2AHB write & read operations are been performed with sequential & non- sequential mode.
Figure 6.4: Simulation of AXI2AHB Bridge
In Simulation ‘Hwdata’ is same as ‘Prdata’ & ‘Hrdata’ is same as ‘Pwdata’ for all various address, it shows correct simulation.
Figure 6.5: Vertex4 FPGA implementation
Figure above is FPGA implementation of presented work method of validation.
6.2 Comparative Results
Table 6.2 Comparative results Parameters Nikhil
Gaikwad et al [1]
Ckristian Duran et al [2]
Chenghai Ma et al [3]
Varsha
vishwarkama et al [4]
Proposed
Slices 79 77 132 NA 57
Max freq. 250.12 MHz
256.57 Mhz 243.3090 Mhz
115.401MHz 316.250 MHz
Figure 6.6: Frequency comparison 0
50 100 150 200 250 300 350
Nikhil Gaikwad et al [1]
Ckristian Duran et al [2]
Chenghai Ma et al [3]
Varsha vishwarkama et
al [4]
Proposed
250.12 256.57
243.309
115.4
316.25
Max freq. (MHz)
Figure 6.7: Area Comparison Form table above & figure above its may
be monitor that number of slices in presented design for vertex FPGA is less as compare with base work by Chenghai Ma et al [2] & Ckristian Duran et al [1], As in vertex FPGA 1 slice is equals to 2 LUT
& 1 flip flop and, LUT of Vertex FPGA has 4 input & 1 output PLA, hence in presented work for 57 slice total 114 LUT’s or 4x1 PLA used & total 57 flip flop used.
In Chenghai Ma works total 132 slices used means 264 LUT’s & 132 flip flops used. In Ckristian Duran works total 77 slices used means 154 LUT’s &
77 flip flops used. Extreme frequency obtain in presented design is high as compare with available work.
7. CONCLUSION
Thesis work was an idea after study many research paper that implementation of protocol interface any kind of various protocol necessary FIFO (First in first out) data structure memory & if we could reduce that FIFO requirement any how we may have a new design with lot less area then it was before. To achieve that first presented design is a new handshaking signals in-between two protocol & then after implement it with help of Mealy kind of FSM. & implementation was with all VLSI design flow right from requirement to validation.
0 20 40 60 80 100 120 140
Nikhil Gaikwad et al [1]
Ckristian Duran et al [2]
Chenghai Ma et al [3]
Proposed
79 77
132
57
