A CRITICAL REVIEW ON SIGNED DIGIT ARITHMETIC’S
1Mr. Sandeep Kumar Dinkar
Asst. Professor, Department of Electronics and Communication Engineering, Laxmi Devi Institute of Engineering & Technology, Alwar
2Sahil Kumar Sharma
Research Scholar, VLSI Design, Department of Electronics and Communication Engineering, Laxmi Devi Institute of Engineering & Technology, Alwar
Abstract - Many scientific and engineering applications require fast processing of arithmetic operations. With the development of VLSI technology an open challenge has been thrown to scientists and engineers to design fast arithmetic operations which can be used in computer with less and less component and time complexity.
Addition is the basic arithmetic operation for all mathematical operations.
Numerous high-speed circuits with regular architectures and low power consumption have been developed as a result of recent advances in integrated circuit technology.
Index Terms: Fast Computing, CSD, HSD, Signed Digit, VLSI and VHDL.
1 INTRODUCTION
Fast computing has become crucial in the domains of research, engineering, and technology. A fast and energy- efficient adder is always required in the electronics industry, particularly in digital signal processing (DSP), image processing, and arithmetic units in microprocessors. Recent advancements in integrated circuit technology have enabled the construction of large-scale arithmetic circuits suitable for VLSI applications.
Numerous computer applications require addition operations, and numerous academics are developing high-speed addition algorithms in response to developments in VLSI technology. In a wide variety of computer applications, addition operations are critical. Carry-free arithmetic operations can be performed utilising an atypical number system to address the growing demand for considerably faster computers. The signed digit number format enables faster addition and subtraction operations in part because there are no carry propagation chains and hence a shorter propagation time. Due to the uniform layout of the SD number system adder, it is well suited for implementation on VLSI devices.
When the current project began, it was created with these concepts in mind. In this paper critical review has been presented which is explained in following sections II to IV.
2 SIGNED DIGIT NUMBER SYSTEM It is possible to classify number systems into two types.Number systems that are not standard include binary, decimal, octal, and hexadecimal, all of which are now in use.
Another system of Number is unconventional in approaches which are as Negative radix no. system and Signed-Digit Number System: RBSD, QSD, CSD, HSD
When performing arithmetic operations, the operands can be represented in a variety of non-binary special number systems [1] in order to reduce or eliminate the delay required by carry propagation. In part due to the removal of the carry propagation chains, the SD number format allows for more rapid addition and subtraction, resulting in superior delay performance overall. Because of signed digit no system, concurrent arithmetic operations in a constant amount of time can be done.
Signed-digit no. system like Redundant Binary Signed Digit no.
system which can have -1, 0, 1 i.e.
three bits to represent any number and Quaternary signed-digit no.
system (QSD) requires (-3,-2,-1, 0, 1, 2, 3) digit set to represent any number.
SD system was invented by Avizienis [1] in 1961, and it has since been explored extensively by a large number of researchers for
applications in trustworthy system design and high-speed multiplication and division algorithms, among other things. Because of the redundancy inherent with signed digit encoding, addition and subtraction are accomplished in a short period of time. This means that the time it takes to add two signed digit integers remains constant regardless of how long the operands are in terms of word length, which is critical for high- speed calculation. If you use the radix r representation of the SD, a single digit can have many 'r' values.
3 QUATERNARY AND HYBRID SIGNED DIGIT NO. SYSTEM
The redundant base four no. system is referred to as quaternary. Increases in the radix typically result in an increase in the degree of redundancy.
QSD numbers are represented using the digit set numbers ranging from -3 to 3. Due to the fact that each number can have various representations, such as RBSD, QSD enables redundancy.
A binary signed binary number system needs two bits to represent a binary signed digit, which slows down the SD number system. The accumulation of time over time requires a lot of physical space to be given up [10]. To make it easier for people to sign some but not all of the digits, this method lets them sign a few but not all of them. To hide the fact that the rest of the digits aren't signed, sign every other digit, or every third or fourth digit, for example. It's useful when you have a lot of data because this format lets you set a maximum length for carry propagation chains. It can take as long as (d+1) for a carry to spread. This is the distance between the two most distant signed digits on either side of the carry. Due to the fact that even though there are 32 digits in total in the word, the 32nd (most important) one is signed.
It is up to the designer to pick the rest of them if that is what they want.
In cases where it isn't important to be consistent, you can sign only the first, second, fourth, eighth, sixteenth, and thirty-second digits. You can leave the rest of the digits unsigned (bits). The
length of the carry propagation chain between consecutive signed digit places affects how long it takes to add a representation like this one (16 digit positions; from the 16th to the 32nd digit in this example). When hybrid number representations are used, it is possible to limit the length of carry propagation chains by adding any value between 1 and the length of a whole word to each of the chains. It doesn't have to be in a certain format for the HSD representation to work.
People can change their representation quickly, but when they combine two HSD numbers, they must add an extra digit to record the result.
This results in a non-uniform representation. If a designer has limited space or knows what the worst-case delay will be, this graph might be useful. As shown in Figure 1, if there is not enough space, the designer can choose a hybrid representation that gives the best implementation, which means the one with the least latency or power consumption. A hybrid representation can be used even if there is a worst- case delay. This means the designer can use it to save space (or power) while still meeting the delay requirement.
4 CRITICAL REVIEW
In practically every mathematical unit, including arithmetic, the addition of two operands is the most often performed operation. Apart from performing simple addition and subtraction operations, two-operand adders are frequently used to do more sophisticated operations like as multiplication and division. As a result, a high-speed two-operand adder is required [6,7]. Fast adders minimise the time required to compute addition by, among other approaches, rewriting the adder equations or making intelligent observations about the adding process. Additionally, adder area is critical, especially for arithmetic circuits that may require a large number of adders. While speed is critical, so is adder area.
Since the creation of digital computers, an abundance of
algorithms for executing fast addition and other arithmetic operations has been created and implemented, and new algorithms are continually being proposed. The rapid advancement of technology utilised to perform fundamental arithmetic operations is the primary reason for the ongoing study and development of new algorithms for performing these operations. When developing algorithms, what is practical in one technology may not be optimal in another. As a result, it is critical to continuously review existing algorithms for various arithmetic operations, as well as their relevance for contemporary technology [11].
Without regard for the technology utilised to execute the algorithm, the performance of a particular algorithm is strongly influenced by its unique qualities as well as the number system used to represent the operands and outputs.
As a result, numerous algorithms have been examined to identify which one performs the best, preferably independently of the implementation technology utilised. This chapter analyses several works on signed digit arithmetic published since 1961 and then provides numerous examples of published addition algorithms.
Arithmetic processors are the components of a digital computer that perform mathematical operations on data. To construct an arithmetic function, it must be founded on the use of efficient algorithms and the construction of efficient logic implementations for those algorithms.
While redundant number systems are inconvenient for manual computations, they have proven helpful in recent decades for the development of high-speed arithmetic computers. Avizienis is widely credited with inventing the RBSD (Redundant Binary Signed digit) numbering method [1]. According to Avizienis, the signed digit representation confines carry propagation during addition and subtraction operations in digital computers to a single location to the left. It is possible to totally avoid carry propagation chains by utilising
redundant operand representations.
Due to the redundancy in the no.
representation, a method of fast arithmatic is possible. Each sum (or difference) digit in this method must be a function of only the digits in two contiguous digital places of the operands. It takes the same amount of time to add signed digit numbers of any length as it does to add two digits in a single operation.
In 1961[1], Avizienis proposed both the RBSD Number System and a set of RBSD laws. Chow and Robertson later presented the concept of RBSD adders in 1978, which was later employed. Shafiqul Khalid and colleagues developed a high-speed parallel complete adder capable of carrying-propagation-free addition of two modified signed quaternary integers in 1997 [10].
In 2005, J. Ghassem [22] and colleagues proposed and refined the concept of a two-valued digit (twit). A twit represents one of two potential integer values. Posibits in the range (0,1) and negabits in the range (-1,0) are two special cases of twits that are frequently employed in two's complement representations and the (n,p) encoding of binary signed numbers, respectively. They investigate the fundamental properties of weighted bit-set (WBS) encodings and show that any redundant number system (e.g., generalised signed-digit and hybrid- redundant systems), including those based on noncontiguous and/or zero- excluded zero-excluded digit sets, can be faithfully represented by WTS encoding. They conclude that in 2006 [23], the authors proposed a universal logic-based architecture for RBSD adder s, which was later approved by the IEEE. Traditional rapid multiplication techniques were found in 1990 to compose partial products in redundant form (carry-save or signed-digit) before finally converting the output to conventional format.
This phase is performed in a VLSI implementation by utilising a carry- propagate adder, which is relatively sluggish and takes a substantial amount of chip space. The researchers introduced LRCF-left-to-
right carry free multiplication, which eliminates the carry-propagate phase entirely. The most significant bit is multiplied first in the LRCF algorithm, and the result is then transformed to a standard sign-and-magnitude product (most significant n bits). As a result of the rapid and consistent implementation, it is a great choice for VLSI applications [12].
Rajshekhara and Kal proposed an RBSD adder and multiplier in 1990 [6,7,8] and it has subsequently been widely used. The authors exhibited a high-speed multiplier with redundant binary signed digit number representation and finished with some recommendations. Additionally, they present the logic design of a carry-free redundant binary sign digit (RBSD) adder, a subclass of redundant binary sign digit adder. Their multiplication method, which makes advantage of bit pair recoding, generates the partial product. Following that, the partial products are joined using carry-free RBSD adder s to produce a binary tree that is then displayed on the screen. Due to the regular construction of the RBSD adder , a multiplier appropriate for VLSI implementation can be constructed.
For words of length 'n', the suggested multiplier has a multiplication time of O(log2n) and an area time complexity of O(log2n) (n2log2n).
Later that year, Rajashekhara and Chen [24] proposed alternate Fast Adder and Fast Multiplier designs based on Signed Digit Numbers. They asserted that ternary logic may be used to create a sign digit adder circuit, a claim that is backed up by the literature. The RBSD adder structure was constructed utilising signed-digit numbers with radix 2 and the digit set[-1,0,1], in addition to a MOS/CMOS ternary logic design. The addition of two RBSD numbers in parallel was reported to be possible in three steps without the need for carry propagation. When employed in conjunction with the RBSD number system, ternary logic gave exent results since each ternary bit could represent one of the system's digits.
This offers various advantages over binary logic, which requires more
than one bit to process a single RBSD digit.
The combination of ternary logic and the RBSD number system in this architecture worked effectively because each ternary bit could handle one RBSD digit efficiently. While the RBSD number system allowed for faster add times due to carry free addition, ternary logic simplified the circuit in terms of transistor count and interconnections, making it easily implementable on VLSI platforms.
Ahmed and Awwal developed a high-speed multiplier in 1993 using the recoded modified-signed digit binary number system [9]. Carry propagation is not an issue with the RBSD format since each digit is represented by one of the numbers 0, 1, or -1, which can be recoded into a new form that is not affected by carry propagation when combined together.
Carry propagation is impossible since the recoded number contains no consecutive 1's or -l's. Carry-free adders can be utilised as the fundamental building blocks of a high-speed multiplier when paired with recoded integers, resulting in an array of regular ular structures appropriate for VLSI implementation.
The multiplier consists mostly of two components: a partial product generator and an encoder that converts binary values to recoded binary signed-digits. After that, these RBSD partial products are joined with a recoded carry free adder to create a complete product.
Due to its carry-free addition and subtraction capabilities, redundant arithmetic number systems are gaining popularity in computationally demanding situations. This characteristic permits significantly faster computation of arithmetic operations such as addition, multiplication, division, and square root as compared to conventional binary number systems.
In 1995, Srinivas H.R. and Parhi K.K.
discussed recent breakthroughs in building redundant arithmetic-based addition, multiplication, division, and square root algorithms and structures, which they refer to as
"redundant arithmetic-based
algorithms and structures."
Additionally, there is talk of employing bit/digit-parallel implementations for architectures so that the speed increase achieved through redundant arithmetic is instantly visible, as opposed to bit/digit-serial architectures, the major argument for which is space preservation. Additionally, a new radix 2 division technique is shown that makes advantage of redundant radix 2 quotient digits and needs the use of a two-digit quotient selection function to do the division.
Dhananjay S. Pathak and Israel Koren suggested the Hybrid Signed Digit (HSD) Numbers as a feasible implementation in 1994 [10]. They balance area cost and performance trade-offs while maintaining exent dependability. The characteristics of a hybrid signed digit (HSD) number format were examined, in which certain digits are signed while others remain unsigned. 2 bits are required to express binary form of signed digit in the binary signed digit system in exchange for the SD number system's reduction in addition time, and this amount of space is given up in exchange for continuous addition of time. As an alternative to requiring all digits to be signed, we allow some part of few digits to signed while leaving the remaining digit unsigned.
For e.g., each alternative, third, or fourth digit of a four-digit number can be signed, but the remaining digits can remain unsigned. In this circumstance, the representation is referred to as the Hybrid Signed Digit (HSD). In practise, this proposed number format may be advantageous when a designer's available space is limit and which is known in advance.
When space is restricted, the designer may choose the hybrid representation that results in the best implementation.
Behrooz Parhami [5] also done extensive research on RBSD numbers, publishing substantial work on the subject in 1988, 1993, and 1995.
According to Parhami, the original definition of the sign digit is Arithmetic, which prevents the occurrence of (r = 2), which lacks the
letter "in the permitted range. While it is commonly established that binary signed digit numbers provide limited carry propagation via a little more complicated addition operation, the mechanism by which this occurs is not well understood. A number of important changes are made to the way Arithmetic functions are really implemented in binary signed digit numbers by adopting this "Recoded"
form of binary signed digit numbers, which is introduced by the author.
The author makes various enhancements, including carry-free addition and borrowing-free subtraction, to the original algorithm.
While this technique can be used to speed up intermediate computation results on standard binary computers, its primary application is in the development of special-purpose arithmetic "Engines" that can handle long sequences of computations and operands, such as those involving a large number of digits or computations, as well as those involving a large number of digits and calculations. It is simple binary subtraction that allows RBSD numbers and regular binary numbers to be matched up, which speeds up and simplifies the process of integrating the two systems together (conventional and RBSD). In 2000, Wen-Chang Yeh and Chein-Wei proposed a way for developing a high- speed Booth encoded parallel multiplier [14] based on their past research. We describe a novel Modified Booth Encoding (MBE) technique for partial product manufacturing that outperforms previously published MBE techniques.
In 2002, NurettinBesli and R. G.
Deshmukh proposed a new RBSD Booth's encoding that was adopted [19]. Two topologies are currently popular in parallel multiplier research. The first was introduced by Wallace [2] in 1965 which takes into account i.e. Reduction of partial products and Adding the partial products by fast carry free addition techniques.
Booth demonstrated a technique for halving the quantity of defective products. This approach has
been altered, and the revised procedure requires that the multiplicand be modified such that half of the bits are in principle zero.
This function converts a signed two's radix number to a number system with the digit set -1, 0, 1. Chen and Rajshekhar [8] created a fast multiplier using Signed Digit Numbers and three-valued logic. Because each ternary bit may support one digit, the use of three-valued logic results in a reduction in circuit complexity in terms of transistor count and interconnections. Calculations performed via pipelines can result in substantial time and cost savings.
Pipelining is a well-known hardware design approach that makes use of parallelism to boost a digital system's calculation speed. Due to the simultaneous functioning of all 'n' stages of the pipeline, a pipeline system can operate at 'n' times the computation rate of an equivalent non-pipelined system. A pipelined system's logic is staged using various latch registers. Suggested pipelining technique is for increasing bandwidth by allowing multiple operations to execute concurrently. An RBSD's efficacy Pipelining the various phases improves the multiplier structure, resulting in a decrease in calculation rate. The ability to provide more performance at a lower cost is the primary advantage of pipelining over other parallel design solutions.
In 2004, Daniele Iacono and Marco Ronchi developed a novel high- speed Binary CSD (BCSD) multiplier that makes use of the Canonic Signed Digit (CSD) number system without requiring CSD ternary encoding. The BCSD number system enables the representation of any CSD number using the same word length as the two's complement representation.
Thus, multipliers that employ the BCSD technique have a significant advantage, particularly when the multiplicand is a member of a set of coefficients stored in BCSD notation in memory; in this case, all that is required is a BCSD decoding scheme that converts the BCSD number back to its CSD representation without incurring significant overhead [21].
Sorin Cotofana [13] investigated the implementation of signed digit addition and associated operations using linear threshold networks in the year 2000. The network's depth and size are determined using linear threshold gates.
Ercegovac and colleagues released a research [14] in 2000 arguing for the use of small multipliers to compute various arithmetic functions such as reciprocation, square root, inverse square root, and some elementary functions.
KanikaKaur and Arti Noor (2011) made the following recommendation: Low power consumption has become a primary priority in today's electronics industry. In VLSI chip design, power dissipation has become as critical as performance and size [24]. The primary challenges in shrinking technology below 100nm are power consumption reduction and overall chip power management. Due to the requirement to lower package costs and increase battery life in many systems, power optimization is just as critical as timing optimization.
Leakage current is also critical for power control in low-power VLSI devices. Integrated circuits' total power dissipation is becoming more dominated by leakage current. They discuss many approaches, methodologies, and power management techniques for low-power circuits and systems in their work.
R Uma et al. (2012) made the following proposal: In today's integrated circuits, adders are a common component. The adder must be both fast and efficient in terms of power consumption and chip area.
They discuss the significance of striking a balance between latency, power consumption, and area while designing an adder. The ripple carry adder, carry lookahead adder, carry skip adder, carry select adder, carry increment adder, carry save adder, and carry bypass adder are all used in this research. They examine the module's size, power dissipation, and propagation latency to determine its effectiveness [25].
Mehdi Masoudi et al. (2015) exhibited a variety of fast and energy- efficient full adder designs. The effectiveness of recommended designs was increased by using the unique properties of carbon nanotube FETs (CNTFET). They demonstrate how carbon nanotube field effect transistors can be utilised to create high-speed, low-power complete adder s (CNFET) [26].
Syeda Sharmin and colleagues investigated the Area Efficient Layout Design of Multiply Complements Logic (MCL) Gates using QCA Technology.
Due to its immensely scalable nature and ultra-low power consumption, Quantum dot ular Automata (QCA) is a rapidly evolving technology that is a viable alternative to CMOS. The proposed architectural architecture has a bright future in the development of ultra-low power depletion information processing systems and the ability to accelerate the development of higher digital applications in QCA [27].
Shashi Kant Sharma and Rajesh Mehra contributed to the development of a low-power and area- efficient full adder configuration using 32 nm CMOS technology. In the creation of a wide variety of advanced hardware circuits and processors, full adders are used. In today's technology environment, it is critical to develop a variety of fresh design concepts that conserve energy and space [28].
Soh Hong Teen et al.
demonstrated how to create an IC layout for a decoder using an electric VLSI design technology. The schematic diagram was utilised to create the decoder's whole setup. The simulation results indicated that the layout and schematic circuit of the decoder produced results nearly comparable to those predicted by the theory [29]. Akshay Manjuladevi Rajendra prasad developed a fast testable Radix-2 N-Bit Signed-Digit Adder (2019). By omitting dependent carry chains, the signed-digit representation has been exploited to perform rapid binary addition [30It describes a high-performance radix-2 signed digit architecture that may be easily extended to accommodate 8-bit,
16-bit, 32-bit, and 64-bit signed digit adders, among other features. It is composed of two redundant digital components: a redundant binary to two-s complement converter and a redundant two-s complement adder.
Complement adders, like the two-s complement adder, multiply two operands and output the result in signed-digit format. While utilising the redundant binary to two's complement converter, the redundant binary to two's complement converter's output format is modified.
The two-s complement adder, redundant binary to two-s complement converter, and N-bit signed-digit adder (for N= 8, 16, 32, 64) are rigorously evaluated using a combination of software and custom design optimization.
5 CONCLUSION
Numerous engineers have showed interest in designing and implementing adders. Adders are the fundamental building blocks of mathematical functions, which is why their design has piqued the interest of engineers and specialists working in the fields of microprocessors and signal processors. The majority of techniques to computing and signal processing may be simplified to addition, the most fundamental of all mathematical operations. As a result, rapid adder designs have remained popular in complicated processing applications as a way to reduce the amount of time required to add while retaining performance. Additionally, multiplier s can be used as building blocks for fundamental integer computations such as square, square root, and reciprocal, as well as complex integer computations.
Three different types of number systems are discussed followed by review of the literature: the RBSD, the QSD, and the HDS. In comparison to the QSD number system, the RBSD number system makes use of a smaller digit set (-1, 0, 1), which means that (-3, -2, -1, 0, 1, 2, 3). The number of digits in a QSD increases redundancy, which accelerates addition, but it also increases the complexity of the circuit.
It is also being investigated whether or not the Hybrid Signed Digit (HSD) number representation may be used because increased speed comes at a cost. While the representation of this system can be changed in real time, when two HSD numbers are added, one more digit place is necessary in order to keep the result, resulting in non-uniformity in the representation.
This provides the designer with adequate latitude to decide on and select the appropriate representation for the circuit based on the cost and performance characteristics of the circuit design. It is possible to create the adder and multiplier circuits using the RBSD technique, which takes into consideration each and every variable.
The purpose of this work is to undertake a literature review on fast computing with signed digit number systems such as the RBSD, QSD, and HSD. While QSD is unquestionably quicker than RBSD, the hardware complexity increases due to the higher utilisation of redundant bits in QSD (- 3, -2). In the HSD format, some bits are signed while others are unsigned, which adds complexity and results in irregular layouts.
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