Week-1: Introduction to model checking

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Week-1: Introduction to model checking

B. Srivathsan

Chennai Mathematical Institute

NPTEL-course July - November 2015

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Module 2:

Modeling hardware circuits

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x₁

XOR

x₂ y

0 0 0

0 1 1

1 0 1

1 1 0

x₁ x₂ y

x₁

AND

x₂ y

0 0 0

0 1 0

1 0 0

1 1 1

x₁ x₂ y

x

NOT

y

0 1

1 0

x y

x₁

OR

x₂ y

0 0 0

0 1 1

1 0 1

1 1 1

x₁ x₂ y

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y = NOT ( XOR (x

₁

, x

₂

) )

XOR NOT

x₁

x₂ y

0 0 1

0 1 0

1 0 0

1 1 1

x₁ x₂ y

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y = NOT ( XOR (x

₁

, x

₂

) )

XOR NOT

x₁

x₂ y

0 0 1

0 1 0

1 0 0

1 1 1

x₁ x₂ y

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y = NOT ( XOR (x

₁

, x

₂

) )

XOR NOT

x₁

x₂ y

0 0 1

0 1 0

1 0 0

1 1 1

x₁ x₂ y

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y= NOT(XOR(x,r) )

r_next = XOR(x,r)

XOR NOT

x

_y

r register

Ø Ø Ø Ø Ø Ø Ø Ø Ø

x r y

1 0 0

1 1 1

0

1 0

1

0 0

1

1 1

1 0 0

0 1 0

1 1 1

0 0 1

· · ·

x=0,r=0,y=1 x=1,r=0,y=0

x=0,r=1,y=0 x=1,r=1,y=1

Ø

Ø Ø Ø

Ø

Ø Ø

Ø

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y= NOT(XOR(x,r) ) r_next = XOR(x,r)

XOR NOT

x

_y

r register

x r y

1 0 0

1 1 1

0

1 0

1

0 0

1

1 1

1 0 0

0 1 0

1 1 1

0 0 1

· · ·

x=0,r=0,y=1 x=1,r=0,y=0

x=0,r=1,y=0 x=1,r=1,y=1

Ø

Ø Ø Ø

Ø

Ø Ø

Ø

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XOR NOT

x

_y

r register

x r y

1 0 0

1 1 1

0

1 0

1

0 0

1

1 1

1 0 0

0 1 0

1 1 1

0 0 1

· · ·

x=0,r=0,y=1 x=1,r=0,y=0

x=0,r=1,y=0 x=1,r=1,y=1

Ø

Ø Ø Ø

Ø

Ø Ø

Ø

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XOR NOT

x

_y

r register

x r y

1 0 0

1

1 0

1

0 0

1

1 1

1 0 0

0 1 0

1 1 1

0 0 1

· · ·

x=0,r=0,y=1 x=1,r=0,y=0

x=0,r=1,y=0 x=1,r=1,y=1

Ø

Ø Ø Ø

Ø

Ø Ø

Ø

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XOR NOT

x

_y

r register

x r y

1 0 0

1 1 1

0

1 0

1

0 0

1

1 1

1 0 0

0 1 0

1 1 1

0 0 1

· · ·

x=0,r=0,y=1 x=1,r=0,y=0

x=0,r=1,y=0 x=1,r=1,y=1

Ø

Ø Ø Ø

Ø

Ø Ø

Ø

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XOR NOT

x

_y

r register

x r y

1 0 0

1 1 1

0

1

0

1

0 0

1

1 1

1 0 0

0 1 0

1 1 1

0 0 1

· · ·

x=0,r=0,y=1 x=1,r=0,y=0

x=0,r=1,y=0 x=1,r=1,y=1

Ø

Ø Ø Ø

Ø

Ø Ø

Ø

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XOR NOT

x

_y

r register

x r y

1 0 0

1 1 1

0

1 0

1

0 0

1

1 1

1 0 0

0 1 0

1 1 1

0 0 1

· · ·

x=0,r=0,y=1 x=1,r=0,y=0

x=0,r=1,y=0 x=1,r=1,y=1

Ø

Ø Ø Ø

Ø

Ø Ø

Ø

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XOR NOT

x

_y

r register

x r y

1 0 0

1 1 1

0

1 0

1

0

1

1 1

1 0 0

0 1 0

1 1 1

0 0 1

· · ·

x=0,r=0,y=1 x=1,r=0,y=0

x=0,r=1,y=0 x=1,r=1,y=1

Ø

Ø Ø Ø

Ø

Ø Ø

Ø

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XOR NOT

x

_y

r register

x r y

1 0 0

1 1 1

0

1 0

1

0 0

1

1 1

1 0 0

0 1 0

1 1 1

0 0 1

· · ·

x=0,r=0,y=1 x=1,r=0,y=0

x=0,r=1,y=0 x=1,r=1,y=1

Ø

Ø Ø Ø

Ø

Ø Ø

Ø

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XOR NOT

x

_y

r register

x r y

1 0 0

1 1 1

0

1 0

1

0 0

1

1 0 0

0 1 0

1 1 1

0 0 1

· · ·

x=0,r=0,y=1 x=1,r=0,y=0

x=0,r=1,y=0 x=1,r=1,y=1

Ø

Ø Ø Ø

Ø

Ø Ø

Ø

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XOR NOT

x

_y

r register

x r y

1 0 0

1 1 1

0

1 0

1

0 0

1

1 1

1 0 0

0 1 0

1 1 1

0 0 1

· · ·

x=0,r=0,y=1 x=1,r=0,y=0

x=0,r=1,y=0 x=1,r=1,y=1

Ø

Ø Ø Ø

Ø

Ø Ø

Ø

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XOR NOT

x

_y

r register

x r y

1 0 0

1 1 1

0

1 0

1

0 0

1

1 1

1 0 0

0 1 0

1 1 1

0 0 1

· · ·

x=0,r=0,y=1 x=1,r=0,y=0

x=0,r=1,y=0 x=1,r=1,y=1

Ø

Ø Ø Ø

Ø

Ø Ø

Ø

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XOR NOT

x

_y

r register

x r y

1 0 0

1 1 1

0

1 0

1

0 0

1

1 1

1 0 0

0 1 0

1 1 1

0 0 1

· · ·

x=0,r=0,y=1 x=1,r=0,y=0

x=0,r=1,y=0 x=1,r=1,y=1

Ø

Ø Ø Ø

Ø

Ø Ø

Ø

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XOR NOT

x

_y

r register

x r y

1 0 0

1 1 1

0

1 0

1

0 0

1

1 1

1 0 0

0 1 0

1 1 1

0 0 1

· · ·

x=0,r=0,y=1 x=1,r=0,y=0

x=0,r=1,y=0 x=1,r=1,y=1

Ø

Ø Ø Ø

Ø

Ø Ø

Ø

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XOR NOT

x

_y

r register

x r y

1 0 0

1 1 1

0

1 0

1

0 0

1

1 1

1 0 0

0 1 0

1 1 1

0 0 1

· · ·

x=0,r=0,y=1 x=1,r=0,y=0

x=0,r=1,y=0 x=1,r=1,y=1

Ø

Ø Ø

Ø

Ø Ø

Ø

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XOR NOT

x

_y

r register

x r y

1 0 0

1 1 1

0

1 0

1

0 0

1

1 1

1 0 0

0 1 0

1 1 1

0 0 1

· · ·

x=0,r=0,y=1 x=1,r=0,y=0

x=0,r=1,y=0 x=1,r=1,y=1

Ø

Ø Ø Ø

Ø

Ø Ø

Ø

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XOR NOT

x

_y

r register

x r y

1 0 0

1 1 1

0

1 0

1

0 0

1

1 1

1 0 0

0 1 0

1 1 1

0 0 1

· · ·

x=0,r=0,y=1 x=1,r=0,y=0

x=0,r=1,y=0 x=1,r=1,y=1

Ø

Ø Ø Ø

Ø

Ø Ø

Ø

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x=0,r=0,y=1 x=1,r=0,y=0

x=0,r=1,y=0 x=1,r=1,y=1

Ø

Ø Ø Ø

Ø

Ø Ø

Ø

Non-deterministic transition system

More than one initial state

States with more than one transition on an action

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x=0,r=0,y=1 x=1,r=0,y=0

x=0,r=1,y=0 x=1,r=1,y=1

Ø

Ø Ø Ø

Ø

Ø Ø

Ø

States with more than one transition on an action

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x=0,r=0,y=1 x=1,r=0,y=0

x=0,r=1,y=0 x=1,r=1,y=1

Ø

Ø Ø Ø

Ø

Ø Ø

Ø

States with more than one transition on an action

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Transition Systems

Deterministic Single initial state

and

Non-deterministic Multiple initial states

or

s r s r

₁

r

₂

r

_m

a a

...

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Coming next: examples of deterministic and non-deterministic transition systems

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Non-deterministic

q₀ a q₁

a b

q₀ q₁

q₂ b

b

a a

b a

q₀ a q₁

b b

Deterministic

q₀ a q₁

b b

q₀ q₁

q₂ b

b

a a

c c

q₀ a q₁

b b

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Model of ATM

IDLE PIN? TRAN

BAL DRAW

MORE $$

insert_card

wrong

correct

balance withdrawal

print

amount

cash

no yes

no

Deterministic transition system

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Model of ATM

IDLE PIN? TRAN

BAL DRAW

MORE $$

insert_card

wrong

correct

balance withdrawal

print

amount

cash

no yes

no

Deterministic transition system

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Model of vending machine

IDLE

SELECT

W C

coin

water cola

get_water get_cola

Deterministic transition system

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Model of vending machine

IDLE

SELECT

W C

coin

water cola

get_water get_cola

Deterministic transition system

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Model of hardware circuit

x=0,r=0,y=1 x=1,r=0,y=0

x=0,r=1,y=0 x=1,r=1,y=1

Non-deterministic transition system: to model incomplete information

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Model of hardware circuit

x=0,r=0,y=1 x=1,r=0,y=0

x=0,r=1,y=0 x=1,r=1,y=1

Non-deterministic transition system: to model incomplete information

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Coming next: Another example of hardware circuit

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XOR NOT

OR

r

x y

x=0,r=0,y=1 x=1,r=0,y=0

x=0,r=1,y=0 x=1,r=1,y=1

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Summary

Hardware Circuits

Modeling using transition systems

Non-determinism

Reference:Principles of Model Checking,Baier and Katoen, MIT Press (2008) Pages 26 - 29

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